diff options
-rw-r--r-- | include/dt-bindings/clock/r8a779g0-cpg-mssr.h | 90 | ||||
-rw-r--r-- | include/dt-bindings/power/r8a779g0-sysc.h | 45 |
2 files changed, 135 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r8a779g0-cpg-mssr.h b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h new file mode 100644 index 000000000000..754c54a6eb06 --- /dev/null +++ b/include/dt-bindings/clock/r8a779g0-cpg-mssr.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a779g0 CPG Core Clocks */ + +#define R8A779G0_CLK_ZX 0 +#define R8A779G0_CLK_ZS 1 +#define R8A779G0_CLK_ZT 2 +#define R8A779G0_CLK_ZTR 3 +#define R8A779G0_CLK_S0D2 4 +#define R8A779G0_CLK_S0D3 5 +#define R8A779G0_CLK_S0D4 6 +#define R8A779G0_CLK_S0D1_VIO 7 +#define R8A779G0_CLK_S0D2_VIO 8 +#define R8A779G0_CLK_S0D4_VIO 9 +#define R8A779G0_CLK_S0D8_VIO 10 +#define R8A779G0_CLK_S0D1_VC 11 +#define R8A779G0_CLK_S0D2_VC 12 +#define R8A779G0_CLK_S0D4_VC 13 +#define R8A779G0_CLK_S0D2_MM 14 +#define R8A779G0_CLK_S0D4_MM 15 +#define R8A779G0_CLK_S0D2_U3DG 16 +#define R8A779G0_CLK_S0D4_U3DG 17 +#define R8A779G0_CLK_S0D2_RT 18 +#define R8A779G0_CLK_S0D3_RT 19 +#define R8A779G0_CLK_S0D4_RT 20 +#define R8A779G0_CLK_S0D6_RT 21 +#define R8A779G0_CLK_S0D24_RT 22 +#define R8A779G0_CLK_S0D2_PER 23 +#define R8A779G0_CLK_S0D3_PER 24 +#define R8A779G0_CLK_S0D4_PER 25 +#define R8A779G0_CLK_S0D6_PER 26 +#define R8A779G0_CLK_S0D12_PER 27 +#define R8A779G0_CLK_S0D24_PER 28 +#define R8A779G0_CLK_S0D1_HSC 29 +#define R8A779G0_CLK_S0D2_HSC 30 +#define R8A779G0_CLK_S0D4_HSC 31 +#define R8A779G0_CLK_S0D2_CC 32 +#define R8A779G0_CLK_SVD1_IR 33 +#define R8A779G0_CLK_SVD2_IR 34 +#define R8A779G0_CLK_SVD1_VIP 35 +#define R8A779G0_CLK_SVD2_VIP 36 +#define R8A779G0_CLK_CL 37 +#define R8A779G0_CLK_CL16M 38 +#define R8A779G0_CLK_CL16M_MM 39 +#define R8A779G0_CLK_CL16M_RT 40 +#define R8A779G0_CLK_CL16M_PER 41 +#define R8A779G0_CLK_CL16M_HSC 42 +#define R8A779G0_CLK_Z0 43 +#define R8A779G0_CLK_ZB3 44 +#define R8A779G0_CLK_ZB3D2 45 +#define R8A779G0_CLK_ZB3D4 46 +#define R8A779G0_CLK_ZG 47 +#define R8A779G0_CLK_SD0H 48 +#define R8A779G0_CLK_SD0 49 +#define R8A779G0_CLK_RPC 50 +#define R8A779G0_CLK_RPCD2 51 +#define R8A779G0_CLK_MSO 52 +#define R8A779G0_CLK_CANFD 53 +#define R8A779G0_CLK_CSI 54 +#define R8A779G0_CLK_FRAY 55 +#define R8A779G0_CLK_IPC 56 +#define R8A779G0_CLK_SASYNCRT 57 +#define R8A779G0_CLK_SASYNCPERD1 58 +#define R8A779G0_CLK_SASYNCPERD2 59 +#define R8A779G0_CLK_SASYNCPERD4 60 +#define R8A779G0_CLK_VIOBUS 61 +#define R8A779G0_CLK_VIOBUSD2 62 +#define R8A779G0_CLK_VCBUS 63 +#define R8A779G0_CLK_VCBUSD2 64 +#define R8A779G0_CLK_DSIEXT 65 +#define R8A779G0_CLK_DSIREF 66 +#define R8A779G0_CLK_ADGH 67 +#define R8A779G0_CLK_OSC 68 +#define R8A779G0_CLK_ZR0 69 +#define R8A779G0_CLK_ZR1 70 +#define R8A779G0_CLK_ZR2 71 +#define R8A779G0_CLK_IMPA 72 +#define R8A779G0_CLK_IMPAD4 73 +#define R8A779G0_CLK_CPEX 74 +#define R8A779G0_CLK_CBFUSA 75 +#define R8A779G0_CLK_R 76 + +#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a779g0-sysc.h b/include/dt-bindings/power/r8a779g0-sysc.h new file mode 100644 index 000000000000..7daa70f1814e --- /dev/null +++ b/include/dt-bindings/power/r8a779g0-sysc.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779G0_PD_A1E0D0C0 0 +#define R8A779G0_PD_A1E0D0C1 1 +#define R8A779G0_PD_A1E0D1C0 2 +#define R8A779G0_PD_A1E0D1C1 3 +#define R8A779G0_PD_A2E0D0 16 +#define R8A779G0_PD_A2E0D1 17 +#define R8A779G0_PD_A3E0 20 +#define R8A779G0_PD_A33DGA 24 +#define R8A779G0_PD_A23DGB 25 +#define R8A779G0_PD_A1DSP0 33 +#define R8A779G0_PD_A2IMP01 34 +#define R8A779G0_PD_A2PSC 35 +#define R8A779G0_PD_A2CV0 36 +#define R8A779G0_PD_A2CV1 37 +#define R8A779G0_PD_A1CNN0 41 +#define R8A779G0_PD_A2CN0 42 +#define R8A779G0_PD_A3IR 43 +#define R8A779G0_PD_A1DSP1 45 +#define R8A779G0_PD_A2IMP23 46 +#define R8A779G0_PD_A2DMA 47 +#define R8A779G0_PD_A2CV2 48 +#define R8A779G0_PD_A2CV3 49 +#define R8A779G0_PD_A1DSP2 53 +#define R8A779G0_PD_A1DSP3 54 +#define R8A779G0_PD_A3VIP0 56 +#define R8A779G0_PD_A3VIP1 57 +#define R8A779G0_PD_A3VIP2 58 +#define R8A779G0_PD_A3ISP0 60 +#define R8A779G0_PD_A3ISP1 61 + +/* Always-on power area */ +#define R8A779G0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/ |