diff options
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c | 38 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 5 |
4 files changed, 46 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 2a8007928210..9dd705b985b9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -402,6 +402,44 @@ void get_hdr_visual_confirm_color( } } +void get_subvp_visual_confirm_color( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct tg_color *color) +{ + uint32_t color_value = MAX_TG_COLOR_VALUE; + bool enable_subvp = false; + int i; + + if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx) + return; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe->stream && pipe->stream->mall_stream_config.paired_stream && + pipe->stream->mall_stream_config.type == SUBVP_MAIN) { + /* SubVP enable - red */ + color->color_r_cr = color_value; + enable_subvp = true; + + if (pipe_ctx->stream == pipe->stream) + return; + break; + } + } + + if (enable_subvp && pipe_ctx->stream->mall_stream_config.type == SUBVP_NONE) { + color->color_r_cr = 0; + if (pipe_ctx->stream->ignore_msa_timing_param == 1) + /* SubVP enable and DRR on - green */ + color->color_g_y = color_value; + else + /* SubVP enable and No DRR - blue */ + color->color_b_cb = color_value; + } +} + void get_surface_tile_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ec227e52fdd3..9cde9465f5ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -417,6 +417,7 @@ enum visual_confirm { VISUAL_CONFIRM_SWAPCHAIN = 6, VISUAL_CONFIRM_FAMS = 7, VISUAL_CONFIRM_SWIZZLE = 9, + VISUAL_CONFIRM_SUBVP = 14, }; enum dc_psr_power_opts { diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 3153c9f1c7fa..6271caca4d9a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -2465,6 +2465,8 @@ void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, get_mpctree_visual_confirm_color(pipe_ctx, color); else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) get_surface_tile_visual_confirm_color(pipe_ctx, color); + else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SUBVP) + get_subvp_visual_confirm_color(dc, pipe_ctx, color); if (mpc->funcs->set_bg_color) { memcpy(&pipe_ctx->plane_state->visual_confirm_color, color, sizeof(struct tg_color)); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index a4e02b0ace24..52b4350c9cd8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -273,6 +273,11 @@ void get_surface_visual_confirm_color( const struct pipe_ctx *pipe_ctx, struct tg_color *color); +void get_subvp_visual_confirm_color( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct tg_color *color); + void get_hdr_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color); |