diff options
226 files changed, 8025 insertions, 7214 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fe6b0526b3a6..e17fe2503bba 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -777,9 +777,6 @@ config ARCH_S3C64XX select SAMSUNG_CLKSRC select SAMSUNG_IRQ_VIC_TIMER select S3C_GPIO_TRACK - select S3C_GPIO_PULL_UPDOWN - select S3C_GPIO_CFG_S3C24XX - select S3C_GPIO_CFG_S3C64XX select S3C_DEV_NAND select USB_ARCH_HAS_OHCI select SAMSUNG_GPIOLIB_4BIT @@ -2212,7 +2209,7 @@ menu "Power management options" source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE - depends on !ARCH_S5P64X0 && !ARCH_S5PC100 + depends on !ARCH_S5PC100 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE def_bool y diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index 44013e0672fe..59299ea5b2ff 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig @@ -13,11 +13,16 @@ config CPU_EXYNOS4210 bool select SAMSUNG_DMADEV select ARM_CPU_SUSPEND if PM + select S5P_PM if PM + select S5P_SLEEP if PM help Enable EXYNOS4210 CPU support config SOC_EXYNOS4212 bool + select ARM_CPU_SUSPEND if PM + select S5P_PM if PM + select S5P_SLEEP if PM help Enable EXYNOS4212 SoC support @@ -137,6 +142,14 @@ config MACH_SMDKV310 select S3C_DEV_RTC select S3C_DEV_WDT select S3C_DEV_I2C1 + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_FIMC3 + select S5P_DEV_I2C_HDMIPHY + select S5P_DEV_MFC + select S5P_DEV_TV + select S5P_DEV_USB_EHCI select S3C_DEV_HSMMC select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC2 @@ -151,6 +164,7 @@ config MACH_SMDKV310 select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_KEYPAD select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_USB_PHY help Machine support for Samsung SMDKV310 @@ -176,19 +190,26 @@ config MACH_UNIVERSAL_C210 select S5P_DEV_FIMC1 select S5P_DEV_FIMC2 select S5P_DEV_FIMC3 + select S5P_DEV_CSIS0 + select S5P_DEV_FIMD0 select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 select S3C_DEV_I2C1 select S3C_DEV_I2C3 select S3C_DEV_I2C5 + select S5P_DEV_I2C_HDMIPHY select S5P_DEV_MFC select S5P_DEV_ONENAND + select S5P_DEV_TV select EXYNOS4_DEV_PD + select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_I2C3 select EXYNOS4_SETUP_I2C5 select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_FIMC + select S5P_SETUP_MIPIPHY help Machine support for Samsung Mobile Universal S5PC210 Reference Board. @@ -197,6 +218,8 @@ config MACH_NURI bool "Mobile NURI Board" select CPU_EXYNOS4210 select S3C_DEV_WDT + select S3C_DEV_RTC + select S5P_DEV_FIMD0 select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC3 @@ -206,6 +229,7 @@ config MACH_NURI select S5P_DEV_MFC select S5P_DEV_USB_EHCI select EXYNOS4_DEV_PD + select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_I2C1 select EXYNOS4_SETUP_I2C3 select EXYNOS4_SETUP_I2C5 @@ -221,8 +245,22 @@ config MACH_ORIGEN select CPU_EXYNOS4210 select S3C_DEV_RTC select S3C_DEV_WDT + select S3C_DEV_HSMMC select S3C_DEV_HSMMC2 + select S5P_DEV_FIMC0 + select S5P_DEV_FIMC1 + select S5P_DEV_FIMC2 + select S5P_DEV_FIMC3 + select S5P_DEV_FIMD0 + select S5P_DEV_I2C_HDMIPHY + select S5P_DEV_TV + select S5P_DEV_USB_EHCI + select EXYNOS4_DEV_PD + select SAMSUNG_DEV_BACKLIGHT + select SAMSUNG_DEV_PWM + select EXYNOS4_SETUP_FIMD0 select EXYNOS4_SETUP_SDHCI + select EXYNOS4_SETUP_USB_PHY help Machine support for ORIGEN based on Samsung EXYNOS4210 diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile index c9b2e1f97e44..2bb18f431db9 100644 --- a/arch/arm/mach-exynos4/Makefile +++ b/arch/arm/mach-exynos4/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o -obj-$(CONFIG_PM) += pm.o sleep.o +obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index a52024e309b0..2894f0adef5c 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c @@ -151,6 +151,11 @@ static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable); } +static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable); +} + static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); @@ -191,6 +196,16 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); } +static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); +} + +static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); +} + /* Core list of CMU_CPU side */ static struct clksrc_clk clk_mout_apll = { @@ -508,13 +523,43 @@ static struct clk init_clocks_off[] = { .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 9), }, { + .name = "dac", + .devname = "s5p-sdo", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 2), + }, { + .name = "mixer", + .devname = "s5p-mixer", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 1), + }, { + .name = "vp", + .devname = "s5p-mixer", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "hdmi", + .devname = "exynos4-hdmi", + .enable = exynos4_clk_ip_tv_ctrl, + .ctrlbit = (1 << 3), + }, { + .name = "hdmiphy", + .devname = "exynos4-hdmi", + .enable = exynos4_clk_hdmiphy_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "dacphy", + .devname = "s5p-sdo", + .enable = exynos4_clk_dac_ctrl, + .ctrlbit = (1 << 0), + }, { .name = "dma", - .devname = "s3c-pl330.0", + .devname = "dma-pl330.0", .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 0), }, { .name = "dma", - .devname = "s3c-pl330.1", + .devname = "dma-pl330.1", .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 1), }, { @@ -635,6 +680,12 @@ static struct clk init_clocks_off[] = { .enable = exynos4_clk_ip_peril_ctrl, .ctrlbit = (1 << 13), }, { + .name = "i2c", + .devname = "s3c2440-hdmiphy-i2c", + .parent = &clk_aclk_100.clk, + .enable = exynos4_clk_ip_peril_ctrl, + .ctrlbit = (1 << 14), + }, { .name = "SYSMMU_MDMA", .enable = exynos4_clk_ip_image_ctrl, .ctrlbit = (1 << 5), @@ -836,6 +887,81 @@ static struct clksrc_sources clkset_mout_mfc = { .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list), }; +static struct clk *clkset_sclk_dac_list[] = { + [0] = &clk_sclk_vpll.clk, + [1] = &clk_sclk_hdmiphy, +}; + +static struct clksrc_sources clkset_sclk_dac = { + .sources = clkset_sclk_dac_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list), +}; + +static struct clksrc_clk clk_sclk_dac = { + .clk = { + .name = "sclk_dac", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 8), + }, + .sources = &clkset_sclk_dac, + .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 }, +}; + +static struct clksrc_clk clk_sclk_pixel = { + .clk = { + .name = "sclk_pixel", + .parent = &clk_sclk_vpll.clk, + }, + .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 }, +}; + +static struct clk *clkset_sclk_hdmi_list[] = { + [0] = &clk_sclk_pixel.clk, + [1] = &clk_sclk_hdmiphy, +}; + +static struct clksrc_sources clkset_sclk_hdmi = { + .sources = clkset_sclk_hdmi_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list), +}; + +static struct clksrc_clk clk_sclk_hdmi = { + .clk = { + .name = "sclk_hdmi", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_sclk_hdmi, + .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 }, +}; + +static struct clk *clkset_sclk_mixer_list[] = { + [0] = &clk_sclk_dac.clk, + [1] = &clk_sclk_hdmi.clk, +}; + +static struct clksrc_sources clkset_sclk_mixer = { + .sources = clkset_sclk_mixer_list, + .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), +}; + +static struct clksrc_clk clk_sclk_mixer = { + .clk = { + .name = "sclk_mixer", + .enable = exynos4_clksrc_mask_tv_ctrl, + .ctrlbit = (1 << 4), + }, + .sources = &clkset_sclk_mixer, + .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk *sclk_tv[] = { + &clk_sclk_dac, + &clk_sclk_pixel, + &clk_sclk_hdmi, + &clk_sclk_mixer, +}; + static struct clksrc_clk clk_dout_mmc0 = { .clk = { .name = "dout_mmc0", @@ -1162,6 +1288,71 @@ static struct clk_ops exynos4_fout_apll_ops = { .get_rate = exynos4_fout_apll_get_rate, }; +static u32 vpll_div[][8] = { + { 54000000, 3, 53, 3, 1024, 0, 17, 0 }, + { 108000000, 3, 53, 2, 1024, 0, 17, 0 }, +}; + +static unsigned long exynos4_vpll_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int vpll_con0, vpll_con1 = 0; + unsigned int i; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + vpll_con0 = __raw_readl(S5P_VPLL_CON0); + vpll_con0 &= ~(0x1 << 27 | \ + PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \ + PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \ + PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); + + vpll_con1 = __raw_readl(S5P_VPLL_CON1); + vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \ + PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \ + PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(vpll_div); i++) { + if (vpll_div[i][0] == rate) { + vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT; + vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT; + vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT; + vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT; + vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT; + vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT; + vpll_con0 |= vpll_div[i][7] << 27; + break; + } + } + + if (i == ARRAY_SIZE(vpll_div)) { + printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", + __func__); + return -EINVAL; + } + + __raw_writel(vpll_con0, S5P_VPLL_CON0); + __raw_writel(vpll_con1, S5P_VPLL_CON1); + + /* Wait for VPLL lock */ + while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT))) + continue; + + clk->rate = rate; + return 0; +} + +static struct clk_ops exynos4_vpll_ops = { + .get_rate = exynos4_vpll_get_rate, + .set_rate = exynos4_vpll_set_rate, +}; + void __init_or_cpufreq exynos4_setup_clocks(void) { struct clk *xtal_clk; @@ -1219,6 +1410,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void) clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; + clk_fout_vpll.ops = &exynos4_vpll_ops; clk_fout_vpll.rate = vpll; printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", @@ -1246,7 +1438,10 @@ void __init_or_cpufreq exynos4_setup_clocks(void) } static struct clk *clks[] __initdata = { - /* Nothing here yet */ + &clk_sclk_hdmi27m, + &clk_sclk_hdmiphy, + &clk_sclk_usbphy0, + &clk_sclk_usbphy1, }; #ifdef CONFIG_PM_SLEEP @@ -1280,6 +1475,9 @@ void __init exynos4_register_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) s3c_register_clksrc(sysclks[ptr], 1); + for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) + s3c_register_clksrc(sclk_tv[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c index a348434f17b5..5b1765b37f75 100644 --- a/arch/arm/mach-exynos4/cpu.c +++ b/arch/arm/mach-exynos4/cpu.c @@ -28,6 +28,7 @@ #include <plat/fimc-core.h> #include <plat/iic-core.h> #include <plat/reset.h> +#include <plat/tv-core.h> #include <mach/regs-irq.h> #include <mach/regs-pmu.h> @@ -182,6 +183,7 @@ void __init exynos4_map_io(void) s3c_i2c2_setname("s3c2440-i2c"); s5p_fb_setname(0, "exynos4-fb"); + s5p_hdmi_setname("exynos4-hdmi"); } void __init exynos4_init_clocks(int xtal) diff --git a/arch/arm/mach-exynos4/dma.c b/arch/arm/mach-exynos4/dma.c index d57d66255021..9667c61e64fb 100644 --- a/arch/arm/mach-exynos4/dma.c +++ b/arch/arm/mach-exynos4/dma.c @@ -243,6 +243,7 @@ struct amba_device exynos4_device_pdma1 = { static int __init exynos4_dma_init(void) { amba_device_register(&exynos4_device_pdma0, &iomem_resource); + amba_device_register(&exynos4_device_pdma1, &iomem_resource); return 0; } diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h deleted file mode 100644 index 7dffa83d23ff..000000000000 --- a/arch/arm/mach-exynos4/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_CLKDEV_H__ -#define __MACH_CLKDEV_H__ - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do {} while (0) - -#endif diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h index 2d3f6bcd9bc0..dfd4b7eecb90 100644 --- a/arch/arm/mach-exynos4/include/mach/irqs.h +++ b/arch/arm/mach-exynos4/include/mach/irqs.h @@ -95,7 +95,11 @@ #define IRQ_2D IRQ_SPI(89) #define IRQ_PCIE IRQ_SPI(90) +#define IRQ_MIXER IRQ_SPI(91) +#define IRQ_HDMI IRQ_SPI(92) +#define IRQ_IIC_HDMIPHY IRQ_SPI(93) #define IRQ_MFC IRQ_SPI(94) +#define IRQ_SDO IRQ_SPI(95) #define IRQ_AUDIO_SS IRQ_SPI(96) #define IRQ_I2S0 IRQ_SPI(97) diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h index 9f97eb8499ee..918a979181af 100644 --- a/arch/arm/mach-exynos4/include/mach/map.h +++ b/arch/arm/mach-exynos4/include/mach/map.h @@ -112,6 +112,12 @@ #define EXYNOS4_PA_UART 0x13800000 +#define EXYNOS4_PA_VP 0x12C00000 +#define EXYNOS4_PA_MIXER 0x12C10000 +#define EXYNOS4_PA_SDO 0x12C20000 +#define EXYNOS4_PA_HDMI 0x12D00000 +#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000 + #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) #define EXYNOS4_PA_ADC 0x13910000 @@ -161,6 +167,12 @@ #define S5P_PA_TIMER EXYNOS4_PA_TIMER #define S5P_PA_EHCI EXYNOS4_PA_EHCI +#define S5P_PA_SDO EXYNOS4_PA_SDO +#define S5P_PA_VP EXYNOS4_PA_VP +#define S5P_PA_MIXER EXYNOS4_PA_MIXER +#define S5P_PA_HDMI EXYNOS4_PA_HDMI +#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY + #define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD /* UART */ diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h index 1df3b81f96e8..9d8da51e35ca 100644 --- a/arch/arm/mach-exynos4/include/mach/pm-core.h +++ b/arch/arm/mach-exynos4/include/mach/pm-core.h @@ -14,6 +14,10 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ + +#ifndef __ASM_ARCH_PM_CORE_H +#define __ASM_ARCH_PM_CORE_H __FILE__ + #include <mach/regs-pmu.h> static inline void s3c_pm_debug_init_uart(void) @@ -53,7 +57,9 @@ static inline void s3c_pm_restored_gpios(void) /* nothing here yet */ } -static inline void s3c_pm_saved_gpios(void) +static inline void samsung_pm_saved_gpios(void) { /* nothing here yet */ } + +#endif /* __ASM_ARCH_PM_CORE_H */ diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h index a952904b010e..632dd5630138 100644 --- a/arch/arm/mach-exynos4/include/mach/pmu.h +++ b/arch/arm/mach-exynos4/include/mach/pmu.h @@ -13,6 +13,8 @@ #ifndef __ASM_ARCH_PMU_H #define __ASM_ARCH_PMU_H __FILE__ +#define PMU_TABLE_END NULL + enum sys_powerdown { SYS_AFTR, SYS_LPA, @@ -20,6 +22,11 @@ enum sys_powerdown { NUM_SYS_POWERDOWN, }; +struct exynos4_pmu_conf { + void __iomem *reg; + unsigned int val[NUM_SYS_POWERDOWN]; +}; + extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode); #endif /* __ASM_ARCH_PMU_H */ diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h index cdf9b47c303c..4fff8e938fec 100644 --- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h @@ -25,9 +25,10 @@ #define S5P_USE_STANDBY_WFI0 (1 << 16) #define S5P_USE_STANDBY_WFI1 (1 << 17) +#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18) #define S5P_USE_STANDBY_WFE0 (1 << 24) #define S5P_USE_STANDBY_WFE1 (1 << 25) -#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24)) +#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26) #define S5P_SWRESET S5P_PMUREG(0x0400) @@ -35,15 +36,17 @@ #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) -#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) -#define S5P_USBHOST_PHY_ENABLE (1 << 0) +#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700) +#define S5P_HDMI_PHY_ENABLE (1 << 0) + +#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C) +#define S5P_DAC_PHY_ENABLE (1 << 0) #define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) #define S5P_MIPI_DPHY_ENABLE (1 << 0) #define S5P_MIPI_DPHY_SRESETN (1 << 1) #define S5P_MIPI_DPHY_MRESETN (1 << 2) -#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) #define S5P_INFORM0 S5P_PMUREG(0x0800) #define S5P_INFORM1 S5P_PMUREG(0x0804) #define S5P_INFORM2 S5P_PMUREG(0x0808) @@ -76,7 +79,6 @@ #define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) #define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) #define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) -#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) #define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) #define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) @@ -84,7 +86,6 @@ #define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) #define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) #define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) -#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) #define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) #define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) #define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) @@ -92,14 +93,11 @@ #define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) #define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) #define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) -#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) #define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) #define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) #define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) #define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) #define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) -#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) -#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) #define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) #define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) #define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) @@ -120,7 +118,6 @@ #define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) #define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) #define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) -#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) #define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) @@ -156,7 +153,6 @@ #define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) #define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) #define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) -#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) #define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 @@ -165,4 +161,60 @@ #define S5P_CHECK_SLEEP 0x00000BAD +/* Only for EXYNOS4210 */ +#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) +#define S5P_USBHOST_PHY_ENABLE (1 << 0) + +#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) + +#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) +#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) +#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) +#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) +#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) +#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) + +#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) + +/* Only for EXYNOS4212 */ +#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) +#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) +#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) +#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110) +#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114) +#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C) +#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130) +#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154) +#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174) +#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190) +#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194) +#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198) +#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4) +#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0) +#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4) +#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4) +#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC) +#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C) +#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250) +#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320) +#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344) +#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348) +#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394) +#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0) +#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4) +#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8) +#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC) +#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0) + +#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608) +#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628) +#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08) +#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28) +#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48) +#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68) +#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88) +#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8) +#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) +#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) + #endif /* __ASM_ARCH_REGS_PMU_H */ diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c index 6e0536818bf5..2204911a24e9 100644 --- a/arch/arm/mach-exynos4/mach-nuri.c +++ b/arch/arm/mach-exynos4/mach-nuri.c @@ -32,10 +32,12 @@ #include <asm/mach-types.h> #include <plat/adc.h> +#include <plat/regs-fb-v4.h> #include <plat/regs-serial.h> #include <plat/exynos4.h> #include <plat/cpu.h> #include <plat/devs.h> +#include <plat/fb.h> #include <plat/sdhci.h> #include <plat/ehci.h> #include <plat/clock.h> @@ -199,6 +201,33 @@ static struct platform_device nuri_gpio_keys = { }, }; +/* Frame Buffer */ +static struct s3c_fb_pd_win nuri_fb_win0 = { + .win_mode = { + .left_margin = 64, + .right_margin = 16, + .upper_margin = 64, + .lower_margin = 1, + .hsync_len = 48, + .vsync_len = 3, + .xres = 1280, + .yres = 800, + .refresh = 60, + }, + .max_bpp = 24, + .default_bpp = 16, + .virtual_x = 1280, + .virtual_y = 800, +}; + +static struct s3c_fb_platdata nuri_fb_pdata __initdata = { + .win[0] = &nuri_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | + VIDCON0_CLKSEL_LCD, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, +}; + static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power) { int gpio = EXYNOS4_GPE1(5); @@ -1092,6 +1121,7 @@ static struct platform_device *nuri_devices[] __initdata = { /* Samsung Platform Devices */ &s3c_device_i2c5, /* PMIC should initialize first */ &emmc_fixed_voltage, + &s5p_device_fimd0, &s3c_device_hsmmc0, &s3c_device_hsmmc2, &s3c_device_hsmmc3, @@ -1106,6 +1136,7 @@ static struct platform_device *nuri_devices[] __initdata = { &s5p_device_mfc_l, &s5p_device_mfc_r, &exynos4_device_pd[PD_MFC], + &exynos4_device_pd[PD_LCD0], /* NURI Devices */ &nuri_gpio_keys, @@ -1142,12 +1173,15 @@ static void __init nuri_machine_init(void) i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3)); i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs)); + s5p_fimd0_set_platdata(&nuri_fb_pdata); + nuri_ehci_init(); clk_xusbxti.rate = 24000000; /* Last */ platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices)); s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev; + s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev; } MACHINE_START(NURI, "NURI") diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c index b5f6f38557c9..71db8480bb5a 100644 --- a/arch/arm/mach-exynos4/mach-origen.c +++ b/arch/arm/mach-exynos4/mach-origen.c @@ -14,16 +14,31 @@ #include <linux/platform_device.h> #include <linux/io.h> #include <linux/input.h> +#include <linux/pwm_backlight.h> +#include <linux/gpio_keys.h> +#include <linux/i2c.h> +#include <linux/regulator/machine.h> +#include <linux/mfd/max8997.h> +#include <linux/lcd.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> +#include <video/platform_lcd.h> + #include <plat/regs-serial.h> +#include <plat/regs-fb-v4.h> #include <plat/exynos4.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/sdhci.h> #include <plat/iic.h> +#include <plat/ehci.h> +#include <plat/clock.h> +#include <plat/gpio-cfg.h> +#include <plat/backlight.h> +#include <plat/pd.h> +#include <plat/fb.h> #include <mach/map.h> @@ -72,19 +87,543 @@ static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { }, }; +static struct regulator_consumer_supply __initdata ldo3_consumer[] = { + REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */ +}; +static struct regulator_consumer_supply __initdata ldo6_consumer[] = { + REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */ +}; +static struct regulator_consumer_supply __initdata ldo7_consumer[] = { + REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */ +}; +static struct regulator_consumer_supply __initdata ldo8_consumer[] = { + REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */ +}; +static struct regulator_consumer_supply __initdata ldo9_consumer[] = { + REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ +}; +static struct regulator_consumer_supply __initdata ldo11_consumer[] = { + REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */ +}; +static struct regulator_consumer_supply __initdata ldo14_consumer[] = { + REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ +}; +static struct regulator_consumer_supply __initdata ldo17_consumer[] = { + REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */ +}; +static struct regulator_consumer_supply __initdata buck1_consumer[] = { + REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */ +}; +static struct regulator_consumer_supply __initdata buck2_consumer[] = { + REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */ +}; +static struct regulator_consumer_supply __initdata buck3_consumer[] = { + REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */ +}; +static struct regulator_consumer_supply __initdata buck7_consumer[] = { + REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */ +}; + +static struct regulator_init_data __initdata max8997_ldo1_data = { + .constraints = { + .name = "VDD_ABB_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .state_mem = { + .disabled = 1, + }, + }, +}; + +static struct regulator_init_data __initdata max8997_ldo2_data = { + .constraints = { + .name = "VDD_ALIVE_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .enabled = 1, + }, + }, +}; + +static struct regulator_init_data __initdata max8997_ldo3_data = { + .constraints = { + .name = "VMIPI_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo3_consumer), + .consumer_supplies = ldo3_consumer, +}; + +static struct regulator_init_data __initdata max8997_ldo4_data = { + .constraints = { + .name = "VDD_RTC_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .disabled = 1, + }, + }, +}; + +static struct regulator_init_data __initdata max8997_ldo6_data = { + .constraints = { + .name = "VMIPI_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo6_consumer), + .consumer_supplies = ldo6_consumer, +}; + +static struct regulator_init_data __initdata max8997_ldo7_data = { + .constraints = { + .name = "VDD_AUD_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo7_consumer), + .consumer_supplies = ldo7_consumer, +}; + +static struct regulator_init_data __initdata max8997_ldo8_data = { + .constraints = { + .name = "VADC_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo8_consumer), + .consumer_supplies = ldo8_consumer, +}; + +static struct regulator_init_data __initdata max8997_ldo9_data = { + .constraints = { + .name = "DVDD_SWB_2.8V", + .min_uV = 2800000, + .max_uV = 2800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo9_consumer), + .consumer_supplies = ldo9_consumer, +}; + +static struct regulator_init_data __initdata max8997_ldo10_data = { + .constraints = { + .name = "VDD_PLL_1.1V", + .min_uV = 1100000, + .max_uV = 1100000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .disabled = 1, + }, + }, +}; + +static struct regulator_init_data __initdata max8997_ldo11_data = { + .constraints = { + .name = "VDD_AUD_3V", + .min_uV = 3000000, + .max_uV = 3000000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo11_consumer), + .consumer_supplies = ldo11_consumer, +}; + +static struct regulator_init_data __initdata max8997_ldo14_data = { + .constraints = { + .name = "AVDD18_SWB_1.8V", + .min_uV = 1800000, + .max_uV = 1800000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo14_consumer), + .consumer_supplies = ldo14_consumer, +}; + +static struct regulator_init_data __initdata max8997_ldo17_data = { + .constraints = { + .name = "VDD_SWB_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(ldo17_consumer), + .consumer_supplies = ldo17_consumer, +}; + +static struct regulator_init_data __initdata max8997_ldo21_data = { + .constraints = { + .name = "VDD_MIF_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .disabled = 1, + }, + }, +}; + +static struct regulator_init_data __initdata max8997_buck1_data = { + .constraints = { + .name = "VDD_ARM_1.2V", + .min_uV = 950000, + .max_uV = 1350000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck1_consumer), + .consumer_supplies = buck1_consumer, +}; + +static struct regulator_init_data __initdata max8997_buck2_data = { + .constraints = { + .name = "VDD_INT_1.1V", + .min_uV = 900000, + .max_uV = 1100000, + .always_on = 1, + .boot_on = 1, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck2_consumer), + .consumer_supplies = buck2_consumer, +}; + +static struct regulator_init_data __initdata max8997_buck3_data = { + .constraints = { + .name = "VDD_G3D_1.1V", + .min_uV = 900000, + .max_uV = 1100000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck3_consumer), + .consumer_supplies = buck3_consumer, +}; + +static struct regulator_init_data __initdata max8997_buck5_data = { + .constraints = { + .name = "VDDQ_M1M2_1.2V", + .min_uV = 1200000, + .max_uV = 1200000, + .apply_uV = 1, + .always_on = 1, + .state_mem = { + .disabled = 1, + }, + }, +}; + +static struct regulator_init_data __initdata max8997_buck7_data = { + .constraints = { + .name = "VDD_LCD_3.3V", + .min_uV = 3300000, + .max_uV = 3300000, + .boot_on = 1, + .apply_uV = 1, + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .state_mem = { + .disabled = 1 + }, + }, + .num_consumer_supplies = ARRAY_SIZE(buck7_consumer), + .consumer_supplies = buck7_consumer, +}; + +static struct max8997_regulator_data __initdata origen_max8997_regulators[] = { + { MAX8997_LDO1, &max8997_ldo1_data }, + { MAX8997_LDO2, &max8997_ldo2_data }, + { MAX8997_LDO3, &max8997_ldo3_data }, + { MAX8997_LDO4, &max8997_ldo4_data }, + { MAX8997_LDO6, &max8997_ldo6_data }, + { MAX8997_LDO7, &max8997_ldo7_data }, + { MAX8997_LDO8, &max8997_ldo8_data }, + { MAX8997_LDO9, &max8997_ldo9_data }, + { MAX8997_LDO10, &max8997_ldo10_data }, + { MAX8997_LDO11, &max8997_ldo11_data }, + { MAX8997_LDO14, &max8997_ldo14_data }, + { MAX8997_LDO17, &max8997_ldo17_data }, + { MAX8997_LDO21, &max8997_ldo21_data }, + { MAX8997_BUCK1, &max8997_buck1_data }, + { MAX8997_BUCK2, &max8997_buck2_data }, + { MAX8997_BUCK3, &max8997_buck3_data }, + { MAX8997_BUCK5, &max8997_buck5_data }, + { MAX8997_BUCK7, &max8997_buck7_data }, +}; + +struct max8997_platform_data __initdata origen_max8997_pdata = { + .num_regulators = ARRAY_SIZE(origen_max8997_regulators), + .regulators = origen_max8997_regulators, + + .wakeup = true, + .buck1_gpiodvs = false, + .buck2_gpiodvs = false, + .buck5_gpiodvs = false, + .irq_base = IRQ_GPIO_END + 1, + + .ignore_gpiodvs_side_effect = true, + .buck125_default_idx = 0x0, + + .buck125_gpios[0] = EXYNOS4_GPX0(0), + .buck125_gpios[1] = EXYNOS4_GPX0(1), + .buck125_gpios[2] = EXYNOS4_GPX0(2), + + .buck1_voltage[0] = 1350000, + .buck1_voltage[1] = 1300000, + .buck1_voltage[2] = 1250000, + .buck1_voltage[3] = 1200000, + .buck1_voltage[4] = 1150000, + .buck1_voltage[5] = 1100000, + .buck1_voltage[6] = 1000000, + .buck1_voltage[7] = 950000, + + .buck2_voltage[0] = 1100000, + .buck2_voltage[1] = 1100000, + .buck2_voltage[2] = 1100000, + .buck2_voltage[3] = 1100000, + .buck2_voltage[4] = 1000000, + .buck2_voltage[5] = 1000000, + .buck2_voltage[6] = 1000000, + .buck2_voltage[7] = 1000000, + + .buck5_voltage[0] = 1200000, + .buck5_voltage[1] = 1200000, + .buck5_voltage[2] = 1200000, + .buck5_voltage[3] = 1200000, + .buck5_voltage[4] = 1200000, + .buck5_voltage[5] = 1200000, + .buck5_voltage[6] = 1200000, + .buck5_voltage[7] = 1200000, +}; + +/* I2C0 */ +static struct i2c_board_info i2c0_devs[] __initdata = { + { + I2C_BOARD_INFO("max8997", (0xCC >> 1)), + .platform_data = &origen_max8997_pdata, + .irq = IRQ_EINT(4), + }, +}; + +static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = { + .cd_type = S3C_SDHCI_CD_INTERNAL, + .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, +}; + static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .ext_cd_gpio = EXYNOS4_GPK2(2), - .ext_cd_gpio_invert = 1, + .cd_type = S3C_SDHCI_CD_INTERNAL, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, }; +/* USB EHCI */ +static struct s5p_ehci_platdata origen_ehci_pdata; + +static void __init origen_ehci_init(void) +{ + struct s5p_ehci_platdata *pdata = &origen_ehci_pdata; + + s5p_ehci_set_platdata(pdata); +} + +static struct gpio_keys_button origen_gpio_keys_table[] = { + { + .code = KEY_MENU, + .gpio = EXYNOS4_GPX1(5), + .desc = "gpio-keys: KEY_MENU", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + .debounce_interval = 1, + }, { + .code = KEY_HOME, + .gpio = EXYNOS4_GPX1(6), + .desc = "gpio-keys: KEY_HOME", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + .debounce_interval = 1, + }, { + .code = KEY_BACK, + .gpio = EXYNOS4_GPX1(7), + .desc = "gpio-keys: KEY_BACK", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + .debounce_interval = 1, + }, { + .code = KEY_UP, + .gpio = EXYNOS4_GPX2(0), + .desc = "gpio-keys: KEY_UP", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + .debounce_interval = 1, + }, { + .code = KEY_DOWN, + .gpio = EXYNOS4_GPX2(1), + .desc = "gpio-keys: KEY_DOWN", + .type = EV_KEY, + .active_low = 1, + .wakeup = 1, + .debounce_interval = 1, + }, +}; + +static struct gpio_keys_platform_data origen_gpio_keys_data = { + .buttons = origen_gpio_keys_table, + .nbuttons = ARRAY_SIZE(origen_gpio_keys_table), +}; + +static struct platform_device origen_device_gpiokeys = { + .name = "gpio-keys", + .dev = { + .platform_data = &origen_gpio_keys_data, + }, +}; + +static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power) +{ + int ret; + + if (power) + ret = gpio_request_one(EXYNOS4_GPE3(4), + GPIOF_OUT_INIT_HIGH, "GPE3_4"); + else + ret = gpio_request_one(EXYNOS4_GPE3(4), + GPIOF_OUT_INIT_LOW, "GPE3_4"); + + gpio_free(EXYNOS4_GPE3(4)); + + if (ret) + pr_err("failed to request gpio for LCD power: %d\n", ret); +} + +static struct plat_lcd_data origen_lcd_hv070wsa_data = { + .set_power = lcd_hv070wsa_set_power, +}; + +static struct platform_device origen_lcd_hv070wsa = { + .name = "platform-lcd", + .dev.parent = &s5p_device_fimd0.dev, + .dev.platform_data = &origen_lcd_hv070wsa_data, +}; + +static struct s3c_fb_pd_win origen_fb_win0 = { + .win_mode = { + .left_margin = 64, + .right_margin = 16, + .upper_margin = 64, + .lower_margin = 16, + .hsync_len = 48, + .vsync_len = 3, + .xres = 1024, + .yres = 600, + }, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct s3c_fb_platdata origen_lcd_pdata __initdata = { + .win[0] = &origen_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, +}; + static struct platform_device *origen_devices[] __initdata = { &s3c_device_hsmmc2, + &s3c_device_hsmmc0, + &s3c_device_i2c0, &s3c_device_rtc, &s3c_device_wdt, + &s5p_device_ehci, + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, + &s5p_device_fimc3, + &s5p_device_fimd0, + &s5p_device_hdmi, + &s5p_device_i2c_hdmiphy, + &s5p_device_mixer, + &exynos4_device_pd[PD_LCD0], + &exynos4_device_pd[PD_TV], + &origen_device_gpiokeys, + &origen_lcd_hv070wsa, +}; + +/* LCD Backlight data */ +static struct samsung_bl_gpio_info origen_bl_gpio_info = { + .no = EXYNOS4_GPD0(0), + .func = S3C_GPIO_SFN(2), }; +static struct platform_pwm_backlight_data origen_bl_data = { + .pwm_id = 0, + .pwm_period_ns = 1000, +}; + +static void s5p_tv_setup(void) +{ + /* Direct HPD to HDMI chip */ + gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"); + s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); + s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); +} + static void __init origen_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -92,10 +631,42 @@ static void __init origen_map_io(void) s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); } +static void __init origen_power_init(void) +{ + gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ"); + s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf)); + s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE); +} + static void __init origen_machine_init(void) { + origen_power_init(); + + s3c_i2c0_set_platdata(NULL); + i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); + + /* + * Since sdhci instance 2 can contain a bootable media, + * sdhci instance 0 is registered after instance 2. + */ s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); + s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata); + + origen_ehci_init(); + clk_xusbxti.rate = 24000000; + + s5p_tv_setup(); + s5p_i2c_hdmiphy_set_platdata(NULL); + + s5p_fimd0_set_platdata(&origen_lcd_pdata); + platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); + s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev; + + s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev; + s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev; + + samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data); } MACHINE_START(ORIGEN, "ORIGEN") diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c index 2c1a076c6a73..cec2afabe7b4 100644 --- a/arch/arm/mach-exynos4/mach-smdkv310.c +++ b/arch/arm/mach-exynos4/mach-smdkv310.c @@ -37,6 +37,9 @@ #include <plat/pd.h> #include <plat/gpio-cfg.h> #include <plat/backlight.h> +#include <plat/mfc.h> +#include <plat/ehci.h> +#include <plat/clock.h> #include <mach/map.h> @@ -232,17 +235,36 @@ static struct i2c_board_info i2c_devs1[] __initdata = { {I2C_BOARD_INFO("wm8994", 0x1a),}, }; +/* USB EHCI */ +static struct s5p_ehci_platdata smdkv310_ehci_pdata; + +static void __init smdkv310_ehci_init(void) +{ + struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata; + + s5p_ehci_set_platdata(pdata); +} + static struct platform_device *smdkv310_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_hsmmc2, &s3c_device_hsmmc3, &s3c_device_i2c1, + &s5p_device_i2c_hdmiphy, &s3c_device_rtc, &s3c_device_wdt, + &s5p_device_ehci, + &s5p_device_fimc0, + &s5p_device_fimc1, + &s5p_device_fimc2, + &s5p_device_fimc3, &exynos4_device_ac97, &exynos4_device_i2s0, &samsung_device_keypad, + &s5p_device_mfc, + &s5p_device_mfc_l, + &s5p_device_mfc_r, &exynos4_device_pd[PD_MFC], &exynos4_device_pd[PD_G3D], &exynos4_device_pd[PD_LCD0], @@ -258,6 +280,8 @@ static struct platform_device *smdkv310_devices[] __initdata = { &smdkv310_lcd_lte480wv, &smdkv310_smsc911x, &exynos4_device_ahci, + &s5p_device_hdmi, + &s5p_device_mixer, }; static void __init smdkv310_smsc911x_init(void) @@ -294,6 +318,18 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = { .pwm_period_ns = 1000, }; +static void s5p_tv_setup(void) +{ + /* direct HPD to HDMI chip */ + WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug")); + s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); + s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); + + /* setup dependencies between TV devices */ + s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev; + s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev; +} + static void __init smdkv310_map_io(void) { s5p_init_io(NULL, 0, S5P_VA_CHIPID); @@ -301,6 +337,11 @@ static void __init smdkv310_map_io(void) s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs)); } +static void __init smdkv310_reserve(void) +{ + s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); +} + static void __init smdkv310_machine_init(void) { s3c_i2c1_set_platdata(NULL); @@ -313,12 +354,19 @@ static void __init smdkv310_machine_init(void) s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata); s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata); + s5p_tv_setup(); + s5p_i2c_hdmiphy_set_platdata(NULL); + samsung_keypad_set_platdata(&smdkv310_keypad_data); samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data); s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata); + smdkv310_ehci_init(); + clk_xusbxti.rate = 24000000; + platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices)); + s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev; } MACHINE_START(SMDKV310, "SMDKV310") @@ -329,6 +377,7 @@ MACHINE_START(SMDKV310, "SMDKV310") .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, .timer = &exynos4_timer, + .reserve = &smdkv310_reserve, MACHINE_END MACHINE_START(SMDKC210, "SMDKC210") diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c index 2aac6f755c8e..a2a177ff4b44 100644 --- a/arch/arm/mach-exynos4/mach-universal_c210.c +++ b/arch/arm/mach-exynos4/mach-universal_c210.c @@ -13,6 +13,7 @@ #include <linux/i2c.h> #include <linux/gpio_keys.h> #include <linux/gpio.h> +#include <linux/fb.h> #include <linux/mfd/max8998.h> #include <linux/regulator/machine.h> #include <linux/regulator/fixed.h> @@ -31,12 +32,21 @@ #include <plat/devs.h> #include <plat/iic.h> #include <plat/gpio-cfg.h> +#include <plat/fb.h> #include <plat/mfc.h> #include <plat/sdhci.h> #include <plat/pd.h> +#include <plat/regs-fb-v4.h> +#include <plat/fimc-core.h> +#include <plat/camport.h> +#include <plat/mipi_csis.h> #include <mach/map.h> +#include <media/v4l2-mediabus.h> +#include <media/s5p_fimc.h> +#include <media/m5mols.h> + /* Following are default values for UCON, ULCON and UFCON UART registers */ #define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ @@ -110,6 +120,9 @@ static struct regulator_consumer_supply lp3974_buck1_consumer = static struct regulator_consumer_supply lp3974_buck2_consumer = REGULATOR_SUPPLY("vddg3d", NULL); +static struct regulator_consumer_supply lp3974_buck3_consumer = + REGULATOR_SUPPLY("vdet", "s5p-sdo"); + static struct regulator_init_data lp3974_buck1_data = { .constraints = { .name = "VINT_1.1V", @@ -153,6 +166,8 @@ static struct regulator_init_data lp3974_buck3_data = { .enabled = 1, }, }, + .num_consumer_supplies = 1, + .consumer_supplies = &lp3974_buck3_consumer, }; static struct regulator_init_data lp3974_buck4_data = { @@ -181,6 +196,12 @@ static struct regulator_init_data lp3974_ldo2_data = { }, }; +static struct regulator_consumer_supply lp3974_ldo3_consumer[] = { + REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), + REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), + REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), +}; + static struct regulator_init_data lp3974_ldo3_data = { .constraints = { .name = "VUSB+MIPI_1.1V", @@ -192,6 +213,12 @@ static struct regulator_init_data lp3974_ldo3_data = { .disabled = 1, }, }, + .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer), + .consumer_supplies = lp3974_ldo3_consumer, +}; + +static struct regulator_consumer_supply lp3974_ldo4_consumer[] = { + REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), }; static struct regulator_init_data lp3974_ldo4_data = { @@ -205,6 +232,8 @@ static struct regulator_init_data lp3974_ldo4_data = { .disabled = 1, }, }, + .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer), + .consumer_supplies = lp3974_ldo4_consumer, }; static struct regulator_init_data lp3974_ldo5_data = { @@ -233,6 +262,10 @@ static struct regulator_init_data lp3974_ldo6_data = { }, }; +static struct regulator_consumer_supply lp3974_ldo7_consumer[] = { + REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), +}; + static struct regulator_init_data lp3974_ldo7_data = { .constraints = { .name = "VLCD+VMIPI_1.8V", @@ -244,6 +277,12 @@ static struct regulator_init_data lp3974_ldo7_data = { .disabled = 1, }, }, + .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer), + .consumer_supplies = lp3974_ldo7_consumer, +}; + +static struct regulator_consumer_supply lp3974_ldo8_consumer[] = { + REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"), }; static struct regulator_init_data lp3974_ldo8_data = { @@ -257,6 +296,8 @@ static struct regulator_init_data lp3974_ldo8_data = { .disabled = 1, }, }, + .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer), + .consumer_supplies = lp3974_ldo8_consumer, }; static struct regulator_init_data lp3974_ldo9_data = { @@ -286,6 +327,9 @@ static struct regulator_init_data lp3974_ldo10_data = { }, }; +static struct regulator_consumer_supply lp3974_ldo11_consumer = + REGULATOR_SUPPLY("dig_28", "0-001f"); + static struct regulator_init_data lp3974_ldo11_data = { .constraints = { .name = "CAM_AF_3.3V", @@ -297,6 +341,8 @@ static struct regulator_init_data lp3974_ldo11_data = { .disabled = 1, }, }, + .num_consumer_supplies = 1, + .consumer_supplies = &lp3974_ldo11_consumer, }; static struct regulator_init_data lp3974_ldo12_data = { @@ -325,6 +371,9 @@ static struct regulator_init_data lp3974_ldo13_data = { }, }; +static struct regulator_consumer_supply lp3974_ldo14_consumer = + REGULATOR_SUPPLY("dig_18", "0-001f"); + static struct regulator_init_data lp3974_ldo14_data = { .constraints = { .name = "CAM_I_HOST_1.8V", @@ -336,8 +385,14 @@ static struct regulator_init_data lp3974_ldo14_data = { .disabled = 1, }, }, + .num_consumer_supplies = 1, + .consumer_supplies = &lp3974_ldo14_consumer, }; + +static struct regulator_consumer_supply lp3974_ldo15_consumer = + REGULATOR_SUPPLY("dig_12", "0-001f"); + static struct regulator_init_data lp3974_ldo15_data = { .constraints = { .name = "CAM_S_DIG+FM33_CORE_1.2V", @@ -349,6 +404,12 @@ static struct regulator_init_data lp3974_ldo15_data = { .disabled = 1, }, }, + .num_consumer_supplies = 1, + .consumer_supplies = &lp3974_ldo15_consumer, +}; + +static struct regulator_consumer_supply lp3974_ldo16_consumer[] = { + REGULATOR_SUPPLY("a_sensor", "0-001f"), }; static struct regulator_init_data lp3974_ldo16_data = { @@ -362,6 +423,8 @@ static struct regulator_init_data lp3974_ldo16_data = { .disabled = 1, }, }, + .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer), + .consumer_supplies = lp3974_ldo16_consumer, }; static struct regulator_init_data lp3974_ldo17_data = { @@ -472,6 +535,43 @@ static struct max8998_platform_data universal_lp3974_pdata = { .wakeup = true, }; + +enum fixed_regulator_id { + FIXED_REG_ID_MMC0, + FIXED_REG_ID_HDMI_5V, + FIXED_REG_ID_CAM_S_IF, + FIXED_REG_ID_CAM_I_CORE, + FIXED_REG_ID_CAM_VT_DIO, +}; + +static struct regulator_consumer_supply hdmi_fixed_consumer = + REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi"); + +static struct regulator_init_data hdmi_fixed_voltage_init_data = { + .constraints = { + .name = "HDMI_5V", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = 1, + .consumer_supplies = &hdmi_fixed_consumer, +}; + +static struct fixed_voltage_config hdmi_fixed_voltage_config = { + .supply_name = "HDMI_EN1", + .microvolts = 5000000, + .gpio = EXYNOS4_GPE0(1), + .enable_high = true, + .init_data = &hdmi_fixed_voltage_init_data, +}; + +static struct platform_device hdmi_fixed_voltage = { + .name = "reg-fixed-voltage", + .id = FIXED_REG_ID_HDMI_5V, + .dev = { + .platform_data = &hdmi_fixed_voltage_config, + }, +}; + /* GPIO I2C 5 (PMIC) */ static struct i2c_board_info i2c5_devs[] __initdata = { { @@ -573,6 +673,11 @@ static void __init universal_touchkey_init(void) gpio_direction_output(gpio, 1); } +static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = { + .frequency = 300 * 1000, + .sda_delay = 200, +}; + /* GPIO KEYS */ static struct gpio_keys_button universal_gpio_keys_tables[] = { { @@ -658,7 +763,7 @@ static struct fixed_voltage_config mmc0_fixed_voltage_config = { static struct platform_device mmc0_fixed_voltage = { .name = "reg-fixed-voltage", - .id = 0, + .id = FIXED_REG_ID_MMC0, .dev = { .platform_data = &mmc0_fixed_voltage_config, }, @@ -692,18 +797,165 @@ static void __init universal_sdhci_init(void) s3c_sdhci3_set_platdata(&universal_hsmmc3_data); } -/* I2C0 */ -static struct i2c_board_info i2c0_devs[] __initdata = { - /* Camera, To be updated */ -}; - /* I2C1 */ static struct i2c_board_info i2c1_devs[] __initdata = { /* Gyro, To be updated */ }; +/* Frame Buffer */ +static struct s3c_fb_pd_win universal_fb_win0 = { + .win_mode = { + .left_margin = 16, + .right_margin = 16, + .upper_margin = 2, + .lower_margin = 28, + .hsync_len = 2, + .vsync_len = 1, + .xres = 480, + .yres = 800, + .refresh = 55, + }, + .max_bpp = 32, + .default_bpp = 16, +}; + +static struct s3c_fb_platdata universal_lcd_pdata __initdata = { + .win[0] = &universal_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB | + VIDCON0_CLKSEL_LCD, + .vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN + | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .setup_gpio = exynos4_fimd0_gpio_setup_24bpp, +}; + +static struct regulator_consumer_supply cam_i_core_supply = + REGULATOR_SUPPLY("core", "0-001f"); + +static struct regulator_init_data cam_i_core_reg_init_data = { + .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, + .num_consumer_supplies = 1, + .consumer_supplies = &cam_i_core_supply, +}; + +static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = { + .supply_name = "CAM_I_CORE_1.2V", + .microvolts = 1200000, + .gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */ + .enable_high = 1, + .init_data = &cam_i_core_reg_init_data, +}; + +static struct platform_device cam_i_core_fixed_reg_dev = { + .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE, + .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg }, +}; + +static struct regulator_consumer_supply cam_s_if_supply = + REGULATOR_SUPPLY("d_sensor", "0-001f"); + +static struct regulator_init_data cam_s_if_reg_init_data = { + .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS }, + .num_consumer_supplies = 1, + .consumer_supplies = &cam_s_if_supply, +}; + +static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = { + .supply_name = "CAM_S_IF_1.8V", + .microvolts = 1800000, + .gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */ + .enable_high = 1, + .init_data = &cam_s_if_reg_init_data, +}; + +static struct platform_device cam_s_if_fixed_reg_dev = { + .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF, + .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg }, +}; + +static struct s5p_platform_mipi_csis mipi_csis_platdata = { + .clk_rate = 166000000UL, + .lanes = 2, + .alignment = 32, + .hs_settle = 12, + .phy_enable = s5p_csis_phy_enable, +}; + +#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3) +#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */ +#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5) + +static int m5mols_set_power(struct device *dev, int on) +{ + gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on); + gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on); + return 0; +} + +static struct m5mols_platform_data m5mols_platdata = { + .gpio_reset = GPIO_CAM_MEGA_nRST, + .reset_polarity = 0, + .set_power = m5mols_set_power, +}; + +static struct i2c_board_info m5mols_board_info = { + I2C_BOARD_INFO("M5MOLS", 0x1F), + .platform_data = &m5mols_platdata, +}; + +static struct s5p_fimc_isp_info universal_camera_sensors[] = { + { + .mux_id = 0, + .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | + V4L2_MBUS_VSYNC_ACTIVE_LOW, + .bus_type = FIMC_MIPI_CSI2, + .board_info = &m5mols_board_info, + .i2c_bus_num = 0, + .clk_frequency = 21600000UL, + .csi_data_align = 32, + }, +}; + +static struct s5p_platform_fimc fimc_md_platdata = { + .isp_info = universal_camera_sensors, + .num_clients = ARRAY_SIZE(universal_camera_sensors), +}; + +static struct gpio universal_camera_gpios[] = { + { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" }, + { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" }, + { GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" }, + { GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" }, +}; + +static void universal_camera_init(void) +{ + s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata), + &s5p_device_mipi_csis0); + s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata), + &s5p_device_fimc_md); + + if (gpio_request_array(universal_camera_gpios, + ARRAY_SIZE(universal_camera_gpios))) { + pr_err("%s: GPIO request failed\n", __func__); + return; + } + + if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf))) + m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT); + else + pr_err("Failed to configure 8M_ISP_INT GPIO\n"); + + /* Free GPIOs controlled directly by the sensor drivers. */ + gpio_free(GPIO_CAM_MEGA_nRST); + gpio_free(GPIO_CAM_8M_ISP_INT); + + if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) + pr_err("Camera port A setup failed\n"); +} + static struct platform_device *universal_devices[] __initdata = { /* Samsung Platform Devices */ + &s5p_device_mipi_csis0, &s5p_device_fimc0, &s5p_device_fimc1, &s5p_device_fimc2, @@ -712,17 +964,30 @@ static struct platform_device *universal_devices[] __initdata = { &s3c_device_hsmmc0, &s3c_device_hsmmc2, &s3c_device_hsmmc3, + &s3c_device_i2c0, &s3c_device_i2c3, &s3c_device_i2c5, + &s5p_device_i2c_hdmiphy, + &hdmi_fixed_voltage, + &exynos4_device_pd[PD_TV], + &s5p_device_hdmi, + &s5p_device_sdo, + &s5p_device_mixer, /* Universal Devices */ &i2c_gpio12, &universal_gpio_keys, &s5p_device_onenand, + &s5p_device_fimd0, &s5p_device_mfc, &s5p_device_mfc_l, &s5p_device_mfc_r, &exynos4_device_pd[PD_MFC], + &exynos4_device_pd[PD_LCD0], + &exynos4_device_pd[PD_CAM], + &cam_i_core_fixed_reg_dev, + &cam_s_if_fixed_reg_dev, + &s5p_device_fimc_md, }; static void __init universal_map_io(void) @@ -732,6 +997,20 @@ static void __init universal_map_io(void) s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs)); } +void s5p_tv_setup(void) +{ + /* direct HPD to HDMI chip */ + gpio_request(EXYNOS4_GPX3(7), "hpd-plug"); + + gpio_direction_input(EXYNOS4_GPX3(7)); + s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3)); + s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE); + + /* setup dependencies between TV devices */ + s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev; + s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev; +} + static void __init universal_reserve(void) { s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20); @@ -740,8 +1019,9 @@ static void __init universal_reserve(void) static void __init universal_machine_init(void) { universal_sdhci_init(); + s5p_tv_setup(); - i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs)); + s3c_i2c0_set_platdata(&universal_i2c0_platdata); i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs)); universal_tsp_init(); @@ -749,15 +1029,28 @@ static void __init universal_machine_init(void) i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs)); s3c_i2c5_set_platdata(NULL); + s5p_i2c_hdmiphy_set_platdata(NULL); i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs)); + s5p_fimd0_set_platdata(&universal_lcd_pdata); + universal_touchkey_init(); i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs, ARRAY_SIZE(i2c_gpio12_devs)); + universal_camera_init(); + /* Last */ platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices)); + s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev; + s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev; + + s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev; + s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev; } MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c index 62e4f4363006..509a435afd4b 100644 --- a/arch/arm/mach-exynos4/pm.c +++ b/arch/arm/mach-exynos4/pm.c @@ -339,6 +339,13 @@ static int exynos4_pm_suspend(void) tmp &= ~S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + if (soc_is_exynos4212()) { + tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION); + tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM | + S5P_USE_STANDBYWFE_ISP_ARM); + __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION); + } + /* Save Power control register */ asm ("mrc p15, 0, %0, c15, c0, 0" : "=r" (tmp) : : "cc"); diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c index 7ea9eb2a20d2..bba48f5c3e8f 100644 --- a/arch/arm/mach-exynos4/pmu.c +++ b/arch/arm/mach-exynos4/pmu.c @@ -16,160 +16,215 @@ #include <mach/regs-clock.h> #include <mach/pmu.h> -static void __iomem *sys_powerdown_reg[] = { - S5P_ARM_CORE0_LOWPWR, - S5P_DIS_IRQ_CORE0, - S5P_DIS_IRQ_CENTRAL0, - S5P_ARM_CORE1_LOWPWR, - S5P_DIS_IRQ_CORE1, - S5P_DIS_IRQ_CENTRAL1, - S5P_ARM_COMMON_LOWPWR, - S5P_L2_0_LOWPWR, - S5P_L2_1_LOWPWR, - S5P_CMU_ACLKSTOP_LOWPWR, - S5P_CMU_SCLKSTOP_LOWPWR, - S5P_CMU_RESET_LOWPWR, - S5P_APLL_SYSCLK_LOWPWR, - S5P_MPLL_SYSCLK_LOWPWR, - S5P_VPLL_SYSCLK_LOWPWR, - S5P_EPLL_SYSCLK_LOWPWR, - S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, - S5P_CMU_RESET_GPSALIVE_LOWPWR, - S5P_CMU_CLKSTOP_CAM_LOWPWR, - S5P_CMU_CLKSTOP_TV_LOWPWR, - S5P_CMU_CLKSTOP_MFC_LOWPWR, - S5P_CMU_CLKSTOP_G3D_LOWPWR, - S5P_CMU_CLKSTOP_LCD0_LOWPWR, - S5P_CMU_CLKSTOP_LCD1_LOWPWR, - S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, - S5P_CMU_CLKSTOP_GPS_LOWPWR, - S5P_CMU_RESET_CAM_LOWPWR, - S5P_CMU_RESET_TV_LOWPWR, - S5P_CMU_RESET_MFC_LOWPWR, - S5P_CMU_RESET_G3D_LOWPWR, - S5P_CMU_RESET_LCD0_LOWPWR, - S5P_CMU_RESET_LCD1_LOWPWR, - S5P_CMU_RESET_MAUDIO_LOWPWR, - S5P_CMU_RESET_GPS_LOWPWR, - S5P_TOP_BUS_LOWPWR, - S5P_TOP_RETENTION_LOWPWR, - S5P_TOP_PWR_LOWPWR, - S5P_LOGIC_RESET_LOWPWR, - S5P_ONENAND_MEM_LOWPWR, - S5P_MODIMIF_MEM_LOWPWR, - S5P_G2D_ACP_MEM_LOWPWR, - S5P_USBOTG_MEM_LOWPWR, - S5P_HSMMC_MEM_LOWPWR, - S5P_CSSYS_MEM_LOWPWR, - S5P_SECSS_MEM_LOWPWR, - S5P_PCIE_MEM_LOWPWR, - S5P_SATA_MEM_LOWPWR, - S5P_PAD_RETENTION_DRAM_LOWPWR, - S5P_PAD_RETENTION_MAUDIO_LOWPWR, - S5P_PAD_RETENTION_GPIO_LOWPWR, - S5P_PAD_RETENTION_UART_LOWPWR, - S5P_PAD_RETENTION_MMCA_LOWPWR, - S5P_PAD_RETENTION_MMCB_LOWPWR, - S5P_PAD_RETENTION_EBIA_LOWPWR, - S5P_PAD_RETENTION_EBIB_LOWPWR, - S5P_PAD_RETENTION_ISOLATION_LOWPWR, - S5P_PAD_RETENTION_ALV_SEL_LOWPWR, - S5P_XUSBXTI_LOWPWR, - S5P_XXTI_LOWPWR, - S5P_EXT_REGULATOR_LOWPWR, - S5P_GPIO_MODE_LOWPWR, - S5P_GPIO_MODE_MAUDIO_LOWPWR, - S5P_CAM_LOWPWR, - S5P_TV_LOWPWR, - S5P_MFC_LOWPWR, - S5P_G3D_LOWPWR, - S5P_LCD0_LOWPWR, - S5P_LCD1_LOWPWR, - S5P_MAUDIO_LOWPWR, - S5P_GPS_LOWPWR, - S5P_GPS_ALIVE_LOWPWR, +static struct exynos4_pmu_conf *exynos4_pmu_config; + +static struct exynos4_pmu_conf exynos4210_pmu_config[] = { + /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ + { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, + { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, + { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } }, + { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } }, + { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, + { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, + { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, + { PMU_TABLE_END,}, }; -static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = { - /* { AFTR, LPA, SLEEP }*/ - { 0, 0, 2 }, /* ARM_CORE0 */ - { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */ - { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */ - { 0, 0, 2 }, /* ARM_CORE1 */ - { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */ - { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */ - { 0, 0, 2 }, /* ARM_COMMON */ - { 2, 2, 3 }, /* ARM_CPU_L2_0 */ - { 2, 2, 3 }, /* ARM_CPU_L2_1 */ - { 1, 0, 0 }, /* CMU_ACLKSTOP */ - { 1, 0, 0 }, /* CMU_SCLKSTOP */ - { 1, 1, 0 }, /* CMU_RESET */ - { 1, 0, 0 }, /* APLL_SYSCLK */ - { 1, 0, 0 }, /* MPLL_SYSCLK */ - { 1, 0, 0 }, /* VPLL_SYSCLK */ - { 1, 1, 0 }, /* EPLL_SYSCLK */ - { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */ - { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */ - { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */ - { 1, 1, 0 }, /* CMU_CLKSTOP_TV */ - { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */ - { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */ - { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */ - { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */ - { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */ - { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */ - { 1, 1, 0 }, /* CMU_RESET_CAM */ - { 1, 1, 0 }, /* CMU_RESET_TV */ - { 1, 1, 0 }, /* CMU_RESET_MFC */ - { 1, 1, 0 }, /* CMU_RESET_G3D */ - { 1, 1, 0 }, /* CMU_RESET_LCD0 */ - { 1, 1, 0 }, /* CMU_RESET_LCD1 */ - { 1, 1, 0 }, /* CMU_RESET_MAUDIO */ - { 1, 1, 0 }, /* CMU_RESET_GPS */ - { 3, 0, 0 }, /* TOP_BUS */ - { 1, 0, 1 }, /* TOP_RETENTION */ - { 3, 0, 3 }, /* TOP_PWR */ - { 1, 1, 0 }, /* LOGIC_RESET */ - { 3, 0, 0 }, /* ONENAND_MEM */ - { 3, 0, 0 }, /* MODIMIF_MEM */ - { 3, 0, 0 }, /* G2D_ACP_MEM */ - { 3, 0, 0 }, /* USBOTG_MEM */ - { 3, 0, 0 }, /* HSMMC_MEM */ - { 3, 0, 0 }, /* CSSYS_MEM */ - { 3, 0, 0 }, /* SECSS_MEM */ - { 3, 0, 0 }, /* PCIE_MEM */ - { 3, 0, 0 }, /* SATA_MEM */ - { 1, 0, 0 }, /* PAD_RETENTION_DRAM */ - { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */ - { 1, 0, 0 }, /* PAD_RETENTION_GPIO */ - { 1, 0, 0 }, /* PAD_RETENTION_UART */ - { 1, 0, 0 }, /* PAD_RETENTION_MMCA */ - { 1, 0, 0 }, /* PAD_RETENTION_MMCB */ - { 1, 0, 0 }, /* PAD_RETENTION_EBIA */ - { 1, 0, 0 }, /* PAD_RETENTION_EBIB */ - { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */ - { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */ - { 1, 1, 0 }, /* XUSBXTI */ - { 1, 1, 0 }, /* XXTI */ - { 1, 1, 0 }, /* EXT_REGULATOR */ - { 1, 0, 0 }, /* GPIO_MODE */ - { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */ - { 7, 0, 0 }, /* CAM */ - { 7, 0, 0 }, /* TV */ - { 7, 0, 0 }, /* MFC */ - { 7, 0, 0 }, /* G3D */ - { 7, 0, 0 }, /* LCD0 */ - { 7, 0, 0 }, /* LCD1 */ - { 7, 7, 0 }, /* MAUDIO */ - { 7, 0, 0 }, /* GPS */ - { 7, 0, 0 }, /* GPS_ALIVE */ +static struct exynos4_pmu_conf exynos4212_pmu_config[] = { + { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, + { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, + { S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } }, + { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } }, + /* XXX_OPTION register should be set other field */ + { S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } }, + { S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } }, + { S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } }, + { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } }, + { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, + { S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } }, + { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } }, + { S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, + { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, + { PMU_TABLE_END,}, }; void exynos4_sys_powerdown_conf(enum sys_powerdown mode) { - unsigned int count = ARRAY_SIZE(sys_powerdown_reg); + unsigned int i; + + for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++) + __raw_writel(exynos4_pmu_config[i].val[mode], + exynos4_pmu_config[i].reg); +} + +static int __init exynos4_pmu_init(void) +{ + exynos4_pmu_config = exynos4210_pmu_config; + + if (soc_is_exynos4210()) { + exynos4_pmu_config = exynos4210_pmu_config; + pr_info("EXYNOS4210 PMU Initialize\n"); + } else if (soc_is_exynos4212()) { + exynos4_pmu_config = exynos4212_pmu_config; + pr_info("EXYNOS4212 PMU Initialize\n"); + } else { + pr_info("EXYNOS4: PMU not supported\n"); + } - for (; count > 0; count--) - __raw_writel(sys_powerdown_val[count - 1][mode], - sys_powerdown_reg[count - 1]); + return 0; } +arch_initcall(exynos4_pmu_init); diff --git a/arch/arm/mach-exynos4/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c index 1e83f8cf236d..92937b410906 100644 --- a/arch/arm/mach-exynos4/setup-sdhci.c +++ b/arch/arm/mach-exynos4/setup-sdhci.c @@ -10,16 +10,7 @@ * published by the Free Software Foundation. */ -#include <linux/kernel.h> #include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <linux/mmc/card.h> -#include <linux/mmc/host.h> - -#include <plat/regs-sdhci.h> /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ @@ -29,41 +20,3 @@ char *exynos4_hsmmc_clksrcs[4] = { [2] = "sclk_mmc", /* mmc_bus */ [3] = NULL, }; - -void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, - struct mmc_ios *ios, struct mmc_card *card) -{ - u32 ctrl2, ctrl3; - - /* don't need to alter anything according to card-type */ - - ctrl2 = readl(r + S3C_SDHCI_CONTROL2); - - /* select base clock source to HCLK */ - - ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; - - /* - * clear async mode, enable conflict mask, rx feedback ctrl, SD - * clk hold and no use debounce count - */ - - ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | - S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | - S3C_SDHCI_CTRL2_DFCNT_NONE | - S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - - /* Tx and Rx feedback clock delay control */ - - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); - - writel(ctrl2, r + S3C_SDHCI_CONTROL2); - writel(ctrl3, r + S3C_SDHCI_CONTROL3); -} diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 3700cf32af0f..5261a7ed0999 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -6,7 +6,6 @@ config CPU_S3C2410 bool depends on ARCH_S3C2410 select CPU_ARM920T - select S3C_GPIO_PULL_UP select S3C2410_CLOCK select CPU_LLSERIAL_S3C2410 select S3C2410_PM if PM diff --git a/arch/arm/mach-s3c2410/include/mach/fb.h b/arch/arm/mach-s3c2410/include/mach/fb.h index eee0654eb8fb..a957bc8ed44f 100644 --- a/arch/arm/mach-s3c2410/include/mach/fb.h +++ b/arch/arm/mach-s3c2410/include/mach/fb.h @@ -1,74 +1 @@ -/* arch/arm/mach-s3c2410/include/mach/fb.h - * - * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org> - * - * Inspired by pxafb.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARM_FB_H -#define __ASM_ARM_FB_H - -#include <mach/regs-lcd.h> - -struct s3c2410fb_hw { - unsigned long lcdcon1; - unsigned long lcdcon2; - unsigned long lcdcon3; - unsigned long lcdcon4; - unsigned long lcdcon5; -}; - -/* LCD description */ -struct s3c2410fb_display { - /* LCD type */ - unsigned type; - - /* Screen size */ - unsigned short width; - unsigned short height; - - /* Screen info */ - unsigned short xres; - unsigned short yres; - unsigned short bpp; - - unsigned pixclock; /* pixclock in picoseconds */ - unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */ - unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */ - unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */ - unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */ - unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */ - unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */ - - /* lcd configuration registers */ - unsigned long lcdcon5; -}; - -struct s3c2410fb_mach_info { - - struct s3c2410fb_display *displays; /* attached diplays info */ - unsigned num_displays; /* number of defined displays */ - unsigned default_display; - - /* GPIOs */ - - unsigned long gpcup; - unsigned long gpcup_mask; - unsigned long gpccon; - unsigned long gpccon_mask; - unsigned long gpdup; - unsigned long gpdup_mask; - unsigned long gpdcon; - unsigned long gpdcon_mask; - - /* lpc3600 control register */ - unsigned long lpcsel; -}; - -extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *); - -#endif /* __ASM_ARM_FB_H */ +#include <plat/fb-s3c2410.h> diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h index bab139201761..c53ad34c6579 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h @@ -1,98 +1 @@ -/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h - * - * Copyright (c) 2003-2009 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - hardware - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __MACH_GPIO_FNS_H -#define __MACH_GPIO_FNS_H __FILE__ - -/* These functions are in the to-be-removed category and it is strongly - * encouraged not to use these in new code. They will be marked deprecated - * very soon. - * - * Most of the functionality can be either replaced by the gpiocfg calls - * for the s3c platform or by the generic GPIOlib API. - * - * As of 2.6.35-rc, these will be removed, with the few drivers using them - * either replaced or given a wrapper until the calls can be removed. -*/ - -#include <plat/gpio-cfg.h> - -static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg) -{ - /* 1:1 mapping between cfgpin and setcfg calls at the moment */ - s3c_gpio_cfgpin(pin, cfg); -} - -/* external functions for GPIO support - * - * These allow various different clients to access the same GPIO - * registers without conflicting. If your driver only owns the entire - * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. -*/ - -extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); - -/* s3c2410_gpio_getirq - * - * turn the given pin number into the corresponding IRQ number - * - * returns: - * < 0 = no interrupt for this pin - * >=0 = interrupt number for the pin -*/ - -extern int s3c2410_gpio_getirq(unsigned int pin); - -/* s3c2410_gpio_irqfilter - * - * set the irq filtering on the given pin - * - * on = 0 => disable filtering - * 1 => enable filtering - * - * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with - * width of filter (0 through 63) - * - * -*/ - -extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, - unsigned int config); - -/* s3c2410_gpio_pullup - * - * This call should be replaced with s3c_gpio_setpull(). - * - * As a note, there is currently no distinction between pull-up and pull-down - * in the s3c24xx series devices with only an on/off configuration. - */ - -/* s3c2410_gpio_pullup - * - * configure the pull-up control on the given pin - * - * to = 1 => disable the pull-up - * 0 => enable the pull-up - * - * eg; - * - * s3c2410_gpio_pullup(S3C2410_GPB(0), 0); - * s3c2410_gpio_pullup(S3C2410_GPE(8), 0); -*/ - -extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); - -extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); - -extern unsigned int s3c2410_gpio_getpin(unsigned int pin); - -#endif /* __MACH_GPIO_FNS_H */ +#include <plat/gpio-fns.h> diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h index d67819dde42a..c410a078622c 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-track.h @@ -17,11 +17,11 @@ #include <mach/regs-gpio.h> -extern struct s3c_gpio_chip s3c24xx_gpios[]; +extern struct samsung_gpio_chip s3c24xx_gpios[]; -static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) +static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin) { - struct s3c_gpio_chip *chip; + struct samsung_gpio_chip *chip; if (pin > S3C_GPIO_END) return NULL; diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index e5a68ea13113..e53b2177319e 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h @@ -191,9 +191,9 @@ #define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 #ifdef CONFIG_CPU_S3C2440 -#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 +#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97 #else -#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97 +#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97 #endif /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 4cf495f813a7..78ae807f1281 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -149,6 +149,7 @@ #define S3C24XX_PA_RTC S3C2410_PA_RTC #define S3C24XX_PA_ADC S3C2410_PA_ADC #define S3C24XX_PA_SPI S3C2410_PA_SPI +#define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1) #define S3C24XX_PA_SDI S3C2410_PA_SDI #define S3C24XX_PA_NAND S3C2410_PA_NAND diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h index 45eea5210c87..2eef7e6f7675 100644 --- a/arch/arm/mach-s3c2410/include/mach/pm-core.h +++ b/arch/arm/mach-s3c2410/include/mach/pm-core.h @@ -64,4 +64,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, } static inline void s3c_pm_restored_gpios(void) { } -static inline void s3c_pm_saved_gpios(void) { } +static inline void samsung_pm_saved_gpios(void) { } diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h index 5e06c7265835..df6434f326f0 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h @@ -102,6 +102,7 @@ #define S3C2443_PCLKCON_UART3 (1<<3) #define S3C2443_PCLKCON_IIC (1<<4) #define S3C2443_PCLKCON_SDI (1<<5) +#define S3C2443_PCLKCON_HSSPI (1<<6) #define S3C2443_PCLKCON_ADC (1<<7) #define S3C2443_PCLKCON_AC97 (1<<8) #define S3C2443_PCLKCON_IIS (1<<9) diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 556c535829f0..caa4ae29ec79 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -696,9 +696,9 @@ static void __init h1940_init(void) S3C2410_MISCCR_USBSUSPND0 | S3C2410_MISCCR_USBSUSPND1, 0x0); - tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT) - | (0x02 << S3C24XX_PLLCON_PDIVSHIFT) - | (0x03 << S3C24XX_PLLCON_SDIVSHIFT); + tmp = (0x78 << S3C24XX_PLL_MDIV_SHIFT) + | (0x02 << S3C24XX_PLL_PDIV_SHIFT) + | (0x03 << S3C24XX_PLL_SDIV_SHIFT); writel(tmp, S3C2410_UPLLCON); gpio_request(S3C2410_GPC(0), "LCD power"); diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 367d376deb96..451852156254 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -49,6 +49,7 @@ #include <mach/regs-gpio.h> #include <mach/leds-gpio.h> +#include <mach/regs-lcd.h> #include <plat/regs-serial.h> #include <mach/fb.h> #include <plat/nand.h> diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index 343a540d86a9..3d7ebc557a72 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -72,8 +72,8 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) void __init s3c2410_map_io(void) { - s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up; - s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up; + s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up; + s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up; iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); } diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c new file mode 100644 index 000000000000..4526f6ba31a8 --- /dev/null +++ b/arch/arm/mach-s3c2412/gpio.c @@ -0,0 +1,62 @@ +/* linux/arch/arm/mach-s3c2412/gpio.c + * + * Copyright (c) 2007 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * http://armlinux.simtec.co.uk/. + * + * S3C2412/S3C2413 specific GPIO support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <mach/regs-gpio.h> +#include <mach/hardware.h> + +#include <plat/gpio-core.h> + +int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) +{ + struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); + unsigned long offs = pin - chip->chip.base; + unsigned long flags; + unsigned long slpcon; + + offs *= 2; + + if (pin < S3C2410_GPB(0)) + return -EINVAL; + + if (pin >= S3C2410_GPF(0) && + pin <= S3C2410_GPG(16)) + return -EINVAL; + + if (pin > S3C2410_GPH(16)) + return -EINVAL; + + local_irq_save(flags); + + slpcon = __raw_readl(chip->base + 0x0C); + + slpcon &= ~(3 << offs); + slpcon |= state << offs; + + __raw_writel(slpcon, chip->base + 0x0C); + + local_irq_restore(flags); + + return 0; +} + +EXPORT_SYMBOL(s3c2412_gpio_set_sleepcfg); diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig index 69b48a7d1dbd..84c7b03e5a30 100644 --- a/arch/arm/mach-s3c2416/Kconfig +++ b/arch/arm/mach-s3c2416/Kconfig @@ -13,7 +13,6 @@ config CPU_S3C2416 select CPU_ARM926T select S3C2416_DMA if S3C2410_DMA select CPU_LLSERIAL_S3C2440 - select S3C_GPIO_PULL_UPDOWN select SAMSUNG_CLKSRC select S3C2443_CLOCK help diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c index 21a5e81f0ab5..72b7c6274c79 100644 --- a/arch/arm/mach-s3c2416/clock.c +++ b/arch/arm/mach-s3c2416/clock.c @@ -21,7 +21,6 @@ #include <plat/cpu.h> #include <plat/cpu-freq.h> -#include <plat/pll6553x.h> #include <plat/pll.h> #include <asm/mach/map.h> @@ -38,6 +37,32 @@ static unsigned int armdiv[8] = { [7] = 8, }; +static struct clksrc_clk hsspi_eplldiv = { + .clk = { + .name = "hsspi-eplldiv", + .parent = &clk_esysclk.clk, + .ctrlbit = (1 << 14), + .enable = s3c2443_clkcon_enable_s, + }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 }, +}; + +static struct clk *hsspi_sources[] = { + [0] = &hsspi_eplldiv.clk, + [1] = NULL, /* to fix */ +}; + +static struct clksrc_clk hsspi_mux = { + .clk = { + .name = "hsspi-if", + }, + .sources = &(struct clksrc_sources) { + .sources = hsspi_sources, + .nr_sources = ARRAY_SIZE(hsspi_sources), + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 }, +}; + static struct clksrc_clk hsmmc_div[] = { [0] = { .clk = { @@ -114,6 +139,8 @@ void __init_or_cpufreq s3c2416_setup_clocks(void) static struct clksrc_clk *clksrcs[] __initdata = { + &hsspi_eplldiv, + &hsspi_mux, &hsmmc_div[0], &hsmmc_div[1], &hsmmc_mux[0], diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index 20b3fdfb3051..7dbee81c8908 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c @@ -120,8 +120,8 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no) void __init s3c2416_map_io(void) { - s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown; - s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown; + s3c24xx_gpiocfg_default.set_pull = samsung_gpio_setpull_updown; + s3c24xx_gpiocfg_default.get_pull = samsung_gpio_getpull_updown; /* initialize device information early */ s3c2416_default_sdhci0(); diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c index ed34fad8f2c6..cee53955eb02 100644 --- a/arch/arm/mach-s3c2416/setup-sdhci.c +++ b/arch/arm/mach-s3c2416/setup-sdhci.c @@ -12,17 +12,7 @@ * published by the Free Software Foundation. */ -#include <linux/kernel.h> #include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <linux/mmc/card.h> -#include <linux/mmc/host.h> - -#include <plat/regs-sdhci.h> -#include <plat/sdhci.h> /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ @@ -32,30 +22,3 @@ char *s3c2416_hsmmc_clksrcs[4] = { [2] = "hsmmc-if", /* [3] = "48m", - note not successfully used yet */ }; - -void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card) -{ - u32 ctrl2, ctrl3; - - ctrl2 = __raw_readl(r + S3C_SDHCI_CONTROL2); - ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; - ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | - S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | - S3C_SDHCI_CTRL2_DFCNT_NONE | - S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); - - __raw_writel(ctrl2, r + S3C_SDHCI_CONTROL2); - __raw_writel(ctrl3, r + S3C_SDHCI_CONTROL3); -} diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index c461fb8e15c0..914e620f1257 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -5,7 +5,6 @@ config CPU_S3C2440 bool select CPU_ARM920T - select S3C_GPIO_PULL_UP select S3C2410_CLOCK select S3C2410_PM if PM select S3C2440_DMA if S3C2410_DMA @@ -17,7 +16,6 @@ config CPU_S3C2440 config CPU_S3C2442 bool select CPU_ARM920T - select S3C_GPIO_PULL_DOWN select S3C2410_CLOCK select S3C2410_PM if PM select CPU_S3C244X diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c index 684dbb3567f5..0d3453bf567c 100644 --- a/arch/arm/mach-s3c2440/mach-rx1950.c +++ b/arch/arm/mach-s3c2440/mach-rx1950.c @@ -43,6 +43,7 @@ #include <mach/regs-gpio.h> #include <mach/regs-gpioj.h> +#include <mach/regs-lcd.h> #include <mach/h1940.h> #include <mach/fb.h> diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c index 2270d3360216..37f8cc6aabd4 100644 --- a/arch/arm/mach-s3c2440/s3c2440.c +++ b/arch/arm/mach-s3c2440/s3c2440.c @@ -70,6 +70,6 @@ void __init s3c2440_map_io(void) { s3c244x_map_io(); - s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up; - s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up; + s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up; + s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up; } diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c index 6f2b65e6e068..2c822e09392f 100644 --- a/arch/arm/mach-s3c2440/s3c2442.c +++ b/arch/arm/mach-s3c2440/s3c2442.c @@ -182,6 +182,6 @@ void __init s3c2442_map_io(void) { s3c244x_map_io(); - s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down; - s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down; + s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1down; + s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1down; } diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig index d8eb86823df7..8814031516ce 100644 --- a/arch/arm/mach-s3c2443/Kconfig +++ b/arch/arm/mach-s3c2443/Kconfig @@ -10,7 +10,6 @@ config CPU_S3C2443 select CPU_LLSERIAL_S3C2440 select SAMSUNG_CLKSRC select S3C2443_CLOCK - select S3C_GPIO_PULL_S3C2443 help Support for the S3C2443 SoC from the S3C24XX line diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 38058af48972..cd51d04e1de7 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -57,10 +57,6 @@ /* clock selections */ -static struct clk clk_i2s_ext = { - .name = "i2s-ext", -}; - /* armdiv * * this clock is sourced from msysclk and can have a number of @@ -173,7 +169,7 @@ static struct clksrc_clk clk_arm = { static struct clksrc_clk clk_hsspi = { .clk = { - .name = "hsspi", + .name = "hsspi-if", .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_HSSPICLK, .enable = s3c2443_clkcon_enable_s, @@ -235,48 +231,6 @@ static struct clk clk_hsmmc = { }, }; -/* i2s_eplldiv - * - * This clock is the output from the I2S divisor of ESYSCLK, and is separate - * from the mux that comes after it (cannot merge into one single clock) -*/ - -static struct clksrc_clk clk_i2s_eplldiv = { - .clk = { - .name = "i2s-eplldiv", - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, -}; - -/* i2s-ref - * - * i2s bus reference clock, selectable from external, esysclk or epllref - * - * Note, this used to be two clocks, but was compressed into one. -*/ - -struct clk *clk_i2s_srclist[] = { - [0] = &clk_i2s_eplldiv.clk, - [1] = &clk_i2s_ext, - [2] = &clk_epllref.clk, - [3] = &clk_epllref.clk, -}; - -static struct clksrc_clk clk_i2s = { - .clk = { - .name = "i2s-if", - .ctrlbit = S3C2443_SCLKCON_I2SCLK, - .enable = s3c2443_clkcon_enable_s, - - }, - .sources = &(struct clksrc_sources) { - .sources = clk_i2s_srclist, - .nr_sources = ARRAY_SIZE(clk_i2s_srclist), - }, - .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 }, -}; - /* standard clock definitions */ static struct clk init_clocks_off[] = { @@ -286,11 +240,6 @@ static struct clk init_clocks_off[] = { .enable = s3c2443_clkcon_enable_p, .ctrlbit = S3C2443_PCLKCON_SDI, }, { - .name = "iis", - .parent = &clk_p, - .enable = s3c2443_clkcon_enable_p, - .ctrlbit = S3C2443_PCLKCON_IIS, - }, { .name = "spi", .devname = "s3c2410-spi.0", .parent = &clk_p, @@ -312,8 +261,6 @@ static struct clk init_clocks[] = { static struct clksrc_clk *clksrcs[] __initdata = { &clk_arm, - &clk_i2s_eplldiv, - &clk_i2s, &clk_hsspi, &clk_hsmmc_div, }; diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index e6a28ba52c7d..5df6458ddd42 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c @@ -90,8 +90,8 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no) void __init s3c2443_map_io(void) { - s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_s3c2443; - s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_s3c2443; + s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull; + s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull; iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); } diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index f057b6ae4f90..5552e048c2be 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig @@ -288,5 +288,6 @@ config MACH_WLF_CRAGG_6410 select S3C_DEV_RTC select S3C64XX_DEV_SPI select S3C24XX_GPIO_EXTRA128 + select I2C help Machine support for the Wolfson Cragganmore S3C6410 variant. diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 61b4034a0c22..cfc0b9941808 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile @@ -13,7 +13,6 @@ obj- := # Core files obj-y += cpu.o obj-y += clock.o -obj-y += gpiolib.o # Core support for S3C6400 system @@ -55,12 +54,10 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o -obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o +obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o # device support obj-y += dev-uart.o obj-y += dev-audio.o obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o -obj-$(CONFIG_S3C64XX_DEV_TS) += dev-ts.o -obj-$(CONFIG_S3C64XX_DEV_ONENAND1) += dev-onenand1.o diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 8cf39e33579e..39c238d7a3dc 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c @@ -25,13 +25,13 @@ #include <mach/regs-sys.h> #include <mach/regs-clock.h> -#include <mach/pll.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/cpu-freq.h> #include <plat/clock.h> #include <plat/clock-clksrc.h> +#include <plat/pll.h> /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call * ext_xtal_mux for want of an actual name from the manual. @@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) /* For now assume the mux always selects the crystal */ clk_ext_xtal_mux.parent = xtal_clk; - epll = s3c6400_get_epll(xtal); + epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0), + __raw_readl(S3C_EPLL_CON1)); mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); @@ -744,7 +745,13 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", apll, mpll, epll); - hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL) + /* Synchronous mode */ + hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + else + /* Asynchronous mode */ + hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); + hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c index c7047838e112..de085b798aa4 100644 --- a/arch/arm/mach-s3c64xx/cpu.c +++ b/arch/arm/mach-s3c64xx/cpu.c @@ -34,8 +34,8 @@ #include <plat/devs.h> #include <plat/clock.h> -#include <mach/s3c6400.h> -#include <mach/s3c6410.h> +#include <plat/s3c6400.h> +#include <plat/s3c6410.h> /* table of supported CPUs */ diff --git a/arch/arm/mach-s3c64xx/dev-onenand1.c b/arch/arm/mach-s3c64xx/dev-onenand1.c deleted file mode 100644 index 999f9e17a1e4..000000000000 --- a/arch/arm/mach-s3c64xx/dev-onenand1.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * linux/arch/arm/mach-s3c64xx/dev-onenand1.c - * - * Copyright (c) 2008-2010 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * S3C64XX series device definition for OneNAND devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/onenand.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/devs.h> - -static struct resource s3c64xx_onenand1_resources[] = { - [0] = { - .start = S3C64XX_PA_ONENAND1, - .end = S3C64XX_PA_ONENAND1 + 0x400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C64XX_PA_ONENAND1_BUF, - .end = S3C64XX_PA_ONENAND1_BUF + S3C64XX_SZ_ONENAND1_BUF - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_ONENAND1, - .end = IRQ_ONENAND1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c64xx_device_onenand1 = { - .name = "samsung-onenand", - .id = 1, - .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources), - .resource = s3c64xx_onenand1_resources, -}; - -void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata) -{ - s3c_set_platdata(pdata, sizeof(struct onenand_platform_data), - &s3c64xx_device_onenand1); -} diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 67c97fab62fd..17d62f4f8204 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c @@ -740,7 +740,7 @@ static int __init s3c64xx_dma_init(void) } /* Set all DMA configuration to be DMA, not SDMA */ - writel(0xffffff, S3C_SYSREG(0x110)); + writel(0xffffff, S3C64XX_SDMA_SEL); /* Register standard DMA controllers */ s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000); diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c deleted file mode 100644 index 92b09085caaa..000000000000 --- a/arch/arm/mach-s3c64xx/gpiolib.c +++ /dev/null @@ -1,290 +0,0 @@ -/* arch/arm/plat-s3c64xx/gpiolib.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - GPIOlib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/gpio.h> - -#include <mach/map.h> - -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> -#include <mach/regs-gpio.h> - -/* GPIO bank summary: - * - * Bank GPIOs Style SlpCon ExtInt Group - * A 8 4Bit Yes 1 - * B 7 4Bit Yes 1 - * C 8 4Bit Yes 2 - * D 5 4Bit Yes 3 - * E 5 4Bit Yes None - * F 16 2Bit Yes 4 [1] - * G 7 4Bit Yes 5 - * H 10 4Bit[2] Yes 6 - * I 16 2Bit Yes None - * J 12 2Bit Yes None - * K 16 4Bit[2] No None - * L 15 4Bit[2] No None - * M 6 4Bit No IRQ_EINT - * N 16 2Bit No IRQ_EINT - * O 16 2Bit Yes 7 - * P 15 2Bit Yes 8 - * Q 9 2Bit Yes 9 - * - * [1] BANKF pins 14,15 do not form part of the external interrupt sources - * [2] BANK has two control registers, GPxCON0 and GPxCON1 - */ - -static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .get_config = s3c_gpio_getcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = { - .cfg_eint = 7, - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .get_config = s3c_gpio_getcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { - .cfg_eint = 3, - .get_config = s3c_gpio_getcfg_s3c64xx_4bit, - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin) -{ - return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; -} - -static struct s3c_gpio_chip gpio_4bit[] = { - { - .base = S3C64XX_GPA_BASE, - .config = &gpio_4bit_cfg_eint0111, - .chip = { - .base = S3C64XX_GPA(0), - .ngpio = S3C64XX_GPIO_A_NR, - .label = "GPA", - }, - }, { - .base = S3C64XX_GPB_BASE, - .config = &gpio_4bit_cfg_eint0111, - .chip = { - .base = S3C64XX_GPB(0), - .ngpio = S3C64XX_GPIO_B_NR, - .label = "GPB", - }, - }, { - .base = S3C64XX_GPC_BASE, - .config = &gpio_4bit_cfg_eint0111, - .chip = { - .base = S3C64XX_GPC(0), - .ngpio = S3C64XX_GPIO_C_NR, - .label = "GPC", - }, - }, { - .base = S3C64XX_GPD_BASE, - .config = &gpio_4bit_cfg_eint0111, - .chip = { - .base = S3C64XX_GPD(0), - .ngpio = S3C64XX_GPIO_D_NR, - .label = "GPD", - }, - }, { - .base = S3C64XX_GPE_BASE, - .config = &gpio_4bit_cfg_noint, - .chip = { - .base = S3C64XX_GPE(0), - .ngpio = S3C64XX_GPIO_E_NR, - .label = "GPE", - }, - }, { - .base = S3C64XX_GPG_BASE, - .config = &gpio_4bit_cfg_eint0111, - .chip = { - .base = S3C64XX_GPG(0), - .ngpio = S3C64XX_GPIO_G_NR, - .label = "GPG", - }, - }, { - .base = S3C64XX_GPM_BASE, - .config = &gpio_4bit_cfg_eint0011, - .chip = { - .base = S3C64XX_GPM(0), - .ngpio = S3C64XX_GPIO_M_NR, - .label = "GPM", - .to_irq = s3c64xx_gpio2int_gpm, - }, - }, -}; - -static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin) -{ - return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; -} - -static struct s3c_gpio_chip gpio_4bit2[] = { - { - .base = S3C64XX_GPH_BASE + 0x4, - .config = &gpio_4bit_cfg_eint0111, - .chip = { - .base = S3C64XX_GPH(0), - .ngpio = S3C64XX_GPIO_H_NR, - .label = "GPH", - }, - }, { - .base = S3C64XX_GPK_BASE + 0x4, - .config = &gpio_4bit_cfg_noint, - .chip = { - .base = S3C64XX_GPK(0), - .ngpio = S3C64XX_GPIO_K_NR, - .label = "GPK", - }, - }, { - .base = S3C64XX_GPL_BASE + 0x4, - .config = &gpio_4bit_cfg_eint0011, - .chip = { - .base = S3C64XX_GPL(0), - .ngpio = S3C64XX_GPIO_L_NR, - .label = "GPL", - .to_irq = s3c64xx_gpio2int_gpl, - }, - }, -}; - -static struct s3c_gpio_cfg gpio_2bit_cfg_noint = { - .set_config = s3c_gpio_setcfg_s3c24xx, - .get_config = s3c_gpio_getcfg_s3c24xx, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = { - .cfg_eint = 2, - .set_config = s3c_gpio_setcfg_s3c24xx, - .get_config = s3c_gpio_getcfg_s3c24xx, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { - .cfg_eint = 3, - .set_config = s3c_gpio_setcfg_s3c24xx, - .get_config = s3c_gpio_getcfg_s3c24xx, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -static struct s3c_gpio_chip gpio_2bit[] = { - { - .base = S3C64XX_GPF_BASE, - .config = &gpio_2bit_cfg_eint11, - .chip = { - .base = S3C64XX_GPF(0), - .ngpio = S3C64XX_GPIO_F_NR, - .label = "GPF", - }, - }, { - .base = S3C64XX_GPI_BASE, - .config = &gpio_2bit_cfg_noint, - .chip = { - .base = S3C64XX_GPI(0), - .ngpio = S3C64XX_GPIO_I_NR, - .label = "GPI", - }, - }, { - .base = S3C64XX_GPJ_BASE, - .config = &gpio_2bit_cfg_noint, - .chip = { - .base = S3C64XX_GPJ(0), - .ngpio = S3C64XX_GPIO_J_NR, - .label = "GPJ", - }, - }, { - .base = S3C64XX_GPN_BASE, - .irq_base = IRQ_EINT(0), - .config = &gpio_2bit_cfg_eint10, - .chip = { - .base = S3C64XX_GPN(0), - .ngpio = S3C64XX_GPIO_N_NR, - .label = "GPN", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = S3C64XX_GPO_BASE, - .config = &gpio_2bit_cfg_eint11, - .chip = { - .base = S3C64XX_GPO(0), - .ngpio = S3C64XX_GPIO_O_NR, - .label = "GPO", - }, - }, { - .base = S3C64XX_GPP_BASE, - .config = &gpio_2bit_cfg_eint11, - .chip = { - .base = S3C64XX_GPP(0), - .ngpio = S3C64XX_GPIO_P_NR, - .label = "GPP", - }, - }, { - .base = S3C64XX_GPQ_BASE, - .config = &gpio_2bit_cfg_eint11, - .chip = { - .base = S3C64XX_GPQ(0), - .ngpio = S3C64XX_GPIO_Q_NR, - .label = "GPQ", - }, - }, -}; - -static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip) -{ - chip->pm = __gpio_pm(&s3c_gpio_pm_2bit); -} - -static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, - int nr_chips, - void (*fn)(struct s3c_gpio_chip *)) -{ - for (; nr_chips > 0; nr_chips--, chips++) { - if (fn) - (fn)(chips); - s3c_gpiolib_add(chips); - } -} - -static __init int s3c64xx_gpiolib_init(void) -{ - s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), - samsung_gpiolib_add_4bit); - - s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), - samsung_gpiolib_add_4bit2); - - s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), - s3c64xx_gpiolib_add_2bit); - - return 0; -} - -core_initcall(s3c64xx_gpiolib_init); diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h deleted file mode 100644 index 7dffa83d23ff..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_CLKDEV_H__ -#define __MACH_CLKDEV_H__ - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do {} while (0) - -#endif diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h new file mode 100644 index 000000000000..be9074e17dfd --- /dev/null +++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h @@ -0,0 +1,23 @@ +/* Cragganmore 6410 shared definitions + * + * Copyright 2011 Wolfson Microelectronics plc + * Mark Brown <broonie@opensource.wolfsonmicro.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef MACH_CRAG6410_H +#define MACH_CRAG6410_H + +#include <linux/gpio.h> + +#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START +#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64) + +#define PCA935X_GPIO_BASE GPIO_BOARD_START +#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8) +#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16) + +#endif diff --git a/arch/arm/mach-s3c64xx/include/mach/pll.h b/arch/arm/mach-s3c64xx/include/mach/pll.h deleted file mode 100644 index 5ef0bb698ee0..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/pll.h +++ /dev/null @@ -1,45 +0,0 @@ -/* arch/arm/plat-s3c64xx/include/plat/pll.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX PLL code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) -#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) -#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) -#define S3C6400_PLL_MDIV_SHIFT (16) -#define S3C6400_PLL_PDIV_SHIFT (8) -#define S3C6400_PLL_SDIV_SHIFT (0) - -#include <asm/div64.h> -#include <plat/pll6553x.h> - -static inline unsigned long s3c6400_get_pll(unsigned long baseclk, - u32 pllcon) -{ - u32 mdiv, pdiv, sdiv; - u64 fvco = baseclk; - - mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK; - pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK; - sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK; - - fvco *= mdiv; - do_div(fvco, (pdiv << sdiv)); - - return (unsigned long)fvco; -} - -static inline unsigned long s3c6400_get_epll(unsigned long baseclk) -{ - return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0), - __raw_readl(S3C_EPLL_CON1)); -} diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h index 38659bebe4b1..fcf3dcabb694 100644 --- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h +++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h @@ -104,7 +104,7 @@ static inline void s3c_pm_restored_gpios(void) __raw_writel(0, S3C64XX_SLPEN); } -static inline void s3c_pm_saved_gpios(void) +static inline void samsung_pm_saved_gpios(void) { /* turn on the sleep mode and keep it there, as it seems that during * suspend the xCON registers get re-set and thus you can end up with diff --git a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h b/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h deleted file mode 100644 index b25bedee0d52..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/pwm-clock.h +++ /dev/null @@ -1,56 +0,0 @@ -/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C64xx - pwm clock and timer support - */ - -/** - * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @tcfg: The timer TCFG1 register bits shifted down to 0. - * - * Return true if the given configuration from TCFG1 is a TCLK instead - * any of the TDIV clocks. - */ -static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) -{ - return tcfg >= S3C64XX_TCFG1_MUX_TCLK; -} - -/** - * tcfg_to_divisor() - convert tcfg1 setting to a divisor - * @tcfg1: The tcfg1 setting, shifted down. - * - * Get the divisor value for the given tcfg1 setting. We assume the - * caller has already checked to see if this is not a TCLK source. - */ -static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) -{ - return 1 << tcfg1; -} - -/** - * pwm_tdiv_has_div1() - does the tdiv setting have a /1 - * - * Return true if we have a /1 in the tdiv setting. - */ -static inline unsigned int pwm_tdiv_has_div1(void) -{ - return 1; -} - -/** - * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. - * @div: The divisor to calculate the bit information for. - * - * Turn a divisor into the necessary bit field for TCFG1. - */ -static inline unsigned long pwm_tdiv_div_bits(unsigned int div) -{ - return ilog2(div); -} - -#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h index 69b78d9f83b8..b91e02093289 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-sys.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-sys.h @@ -21,8 +21,11 @@ #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104) #define S3C64XX_AHB_CON2 S3C_SYSREG(0x108) +#define S3C64XX_SDMA_SEL S3C_SYSREG(0x110) + #define S3C64XX_OTHERS S3C_SYSREG(0x900) #define S3C64XX_OTHERS_USBMASK (1 << 16) +#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6) #endif /* _PLAT_REGS_SYS_H */ diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c index d164a282bfb4..8eba88e7209e 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c64xx/mach-anw6410.c @@ -45,7 +45,7 @@ #include <plat/fb.h> #include <plat/regs-fb-v4.h> -#include <mach/s3c6410.h> +#include <plat/s3c6410.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c new file mode 100644 index 000000000000..66668565ee75 --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c @@ -0,0 +1,182 @@ +/* Speyside modules for Cragganmore - board data probing + * + * Copyright 2011 Wolfson Microelectronics plc + * Mark Brown <broonie@opensource.wolfsonmicro.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> + +#include <linux/mfd/wm831x/irq.h> +#include <linux/mfd/wm831x/gpio.h> + +#include <sound/wm8996.h> +#include <sound/wm8962.h> +#include <sound/wm9081.h> + +#include <mach/crag6410.h> + +static struct wm8996_retune_mobile_config wm8996_retune[] = { + { + .name = "Sub LPF", + .rate = 48000, + .regs = { + 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000, + 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000, + 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000 + }, + }, + { + .name = "Sub HPF", + .rate = 48000, + .regs = { + 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000, + 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000, + 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000 + }, + }, +}; + +static struct wm8996_pdata wm8996_pdata __initdata = { + .ldo_ena = S3C64XX_GPN(7), + .gpio_base = CODEC_GPIO_BASE, + .micdet_def = 1, + .inl_mode = WM8996_DIFFERRENTIAL_1, + .inr_mode = WM8996_DIFFERRENTIAL_1, + + .irq_flags = IRQF_TRIGGER_RISING, + + .gpio_default = { + 0x8001, /* GPIO1 == ADCLRCLK1 */ + 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */ + 0x0141, /* GPIO3 == HP_SEL */ + 0x0002, /* GPIO4 == IRQ */ + 0x020e, /* GPIO5 == CLKOUT */ + }, + + .retune_mobile_cfgs = wm8996_retune, + .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune), +}; + +static struct wm8962_pdata wm8962_pdata __initdata = { + .gpio_init = { + 0, + WM8962_GPIO_FN_OPCLK, + WM8962_GPIO_FN_DMICCLK, + 0, + 0x8000 | WM8962_GPIO_FN_DMICDAT, + WM8962_GPIO_FN_IRQ, /* Open drain mode */ + }, + .irq_active_low = true, +}; + +static struct wm9081_pdata wm9081_pdata __initdata = { + .irq_high = false, + .irq_cmos = false, +}; + +static const struct i2c_board_info wm1254_devs[] = { + { I2C_BOARD_INFO("wm8996", 0x1a), + .platform_data = &wm8996_pdata, + .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, + }, + { I2C_BOARD_INFO("wm9081", 0x6c), + .platform_data = &wm9081_pdata, }, +}; + +static const struct i2c_board_info wm1255_devs[] = { + { I2C_BOARD_INFO("wm5100", 0x1a), + .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, + }, + { I2C_BOARD_INFO("wm9081", 0x6c), + .platform_data = &wm9081_pdata, }, +}; + +static const struct i2c_board_info wm1259_devs[] = { + { I2C_BOARD_INFO("wm8962", 0x1a), + .platform_data = &wm8962_pdata, + .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, + }, +}; + + +static __devinitdata const struct { + u8 id; + const char *name; + const struct i2c_board_info *i2c_devs; + int num_i2c_devs; +} gf_mods[] = { + { .id = 0x01, .name = "1250-EV1 Springbank" }, + { .id = 0x02, .name = "1251-EV1 Jura" }, + { .id = 0x03, .name = "1252-EV1 Glenlivet" }, + { .id = 0x11, .name = "6249-EV2 Glenfarclas", }, + { .id = 0x21, .name = "1275-EV1 Mortlach" }, + { .id = 0x25, .name = "1274-EV1 Glencadam" }, + { .id = 0x31, .name = "1253-EV1 Tomatin", }, + { .id = 0x39, .name = "1254-EV1 Dallas Dhu", + .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) }, + { .id = 0x3a, .name = "1259-EV1 Tobermory", + .i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) }, + { .id = 0x3b, .name = "1255-EV1 Kilchoman", + .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) }, + { .id = 0x3c, .name = "1273-EV1 Longmorn" }, +}; + +static __devinit int wlf_gf_module_probe(struct i2c_client *i2c, + const struct i2c_device_id *i2c_id) +{ + int ret, i, j, id, rev; + + ret = i2c_smbus_read_byte_data(i2c, 0); + if (ret < 0) { + dev_err(&i2c->dev, "Failed to read ID: %d\n", ret); + return ret; + } + + id = (ret & 0xfe) >> 2; + rev = ret & 0x3; + for (i = 0; i < ARRAY_SIZE(gf_mods); i++) + if (id == gf_mods[i].id) + break; + + if (i < ARRAY_SIZE(gf_mods)) { + dev_info(&i2c->dev, "%s revision %d\n", + gf_mods[i].name, rev + 1); + for (j = 0; j < gf_mods[i].num_i2c_devs; j++) { + if (!i2c_new_device(i2c->adapter, + &(gf_mods[i].i2c_devs[j]))) + dev_err(&i2c->dev, + "Failed to register dev: %d\n", ret); + } + } else { + dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n", + id, rev); + } + + return 0; +} + +static const struct i2c_device_id wlf_gf_module_id[] = { + { "wlf-gf-module", 0 }, + { } +}; + +static struct i2c_driver wlf_gf_module_driver = { + .driver = { + .name = "wlf-gf-module", + .owner = THIS_MODULE, + }, + .probe = wlf_gf_module_probe, + .id_table = wlf_gf_module_id, +}; + +static int __init wlf_gf_module_register(void) +{ + return i2c_add_driver(&wlf_gf_module_driver); +} +module_init(wlf_gf_module_register); diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index 806580388f30..d04b65448510 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c @@ -43,13 +43,14 @@ #include <mach/hardware.h> #include <mach/map.h> -#include <mach/s3c6410.h> #include <mach/regs-sys.h> #include <mach/regs-gpio.h> #include <mach/regs-modem.h> +#include <mach/crag6410.h> #include <mach/regs-gpio-memport.h> +#include <plat/s3c6410.h> #include <plat/regs-serial.h> #include <plat/regs-fb-v4.h> #include <plat/fb.h> @@ -65,17 +66,6 @@ #include <plat/iic.h> #include <plat/pm.h> -#include <sound/wm8996.h> -#include <sound/wm8962.h> -#include <sound/wm9081.h> - -#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START -#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64) - -#define PCA935X_GPIO_BASE GPIO_BOARD_START -#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8) -#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16) - /* serial port setup */ #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) @@ -287,6 +277,11 @@ static struct platform_device speyside_device = { .id = -1, }; +static struct platform_device lowland_device = { + .name = "lowland", + .id = -1, +}; + static struct platform_device speyside_wm8962_device = { .name = "speyside-wm8962", .id = -1, @@ -295,6 +290,8 @@ static struct platform_device speyside_wm8962_device = { static struct regulator_consumer_supply wallvdd_consumers[] = { REGULATOR_SUPPLY("SPKVDD1", "1-001a"), REGULATOR_SUPPLY("SPKVDD2", "1-001a"), + REGULATOR_SUPPLY("SPKVDDL", "1-001a"), + REGULATOR_SUPPLY("SPKVDDR", "1-001a"), }; static struct regulator_init_data wallvdd_data = { @@ -342,6 +339,7 @@ static struct platform_device *crag6410_devices[] __initdata = { &crag6410_backlight_device, &speyside_device, &speyside_wm8962_device, + &lowland_device, &wallvdd_device, }; @@ -350,6 +348,12 @@ static struct pca953x_platform_data crag6410_pca_data = { .irq_base = 0, }; +/* VDDARM is controlled by DVS1 connected to GPK(0) */ +static struct wm831x_buckv_pdata vddarm_pdata = { + .dvs_control_src = 1, + .dvs_gpio = S3C64XX_GPK(0), +}; + static struct regulator_consumer_supply vddarm_consumers[] __initdata = { REGULATOR_SUPPLY("vddarm", NULL), }; @@ -365,6 +369,7 @@ static struct regulator_init_data vddarm __initdata = { .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers), .consumer_supplies = vddarm_consumers, .supply_regulator = "WALLVDD", + .driver_data = &vddarm_pdata, }; static struct regulator_init_data vddint __initdata = { @@ -500,6 +505,8 @@ static struct wm831x_pdata crag_pmic_pdata __initdata = { .backup = &banff_backup_pdata, .gpio_defaults = { + /* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */ + [4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8, /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/ [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6, /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/ @@ -557,8 +564,12 @@ static struct regulator_init_data pvdd_1v2 __initdata = { }; static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = { + REGULATOR_SUPPLY("LDOVDD", "1-001a"), REGULATOR_SUPPLY("PLLVDD", "1-001a"), REGULATOR_SUPPLY("DBVDD", "1-001a"), + REGULATOR_SUPPLY("DBVDD1", "1-001a"), + REGULATOR_SUPPLY("DBVDD2", "1-001a"), + REGULATOR_SUPPLY("DBVDD3", "1-001a"), REGULATOR_SUPPLY("CPVDD", "1-001a"), REGULATOR_SUPPLY("AVDD2", "1-001a"), REGULATOR_SUPPLY("DCVDD", "1-001a"), @@ -611,81 +622,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = { .disable_touch = true, }; -static struct wm8996_retune_mobile_config wm8996_retune[] = { - { - .name = "Sub LPF", - .rate = 48000, - .regs = { - 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000, - 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000, - 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000 - }, - }, - { - .name = "Sub HPF", - .rate = 48000, - .regs = { - 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000, - 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000, - 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000 - }, - }, -}; - -static struct wm8996_pdata wm8996_pdata __initdata = { - .ldo_ena = S3C64XX_GPN(7), - .gpio_base = CODEC_GPIO_BASE, - .micdet_def = 1, - .inl_mode = WM8996_DIFFERRENTIAL_1, - .inr_mode = WM8996_DIFFERRENTIAL_1, - - .irq_flags = IRQF_TRIGGER_RISING, - - .gpio_default = { - 0x8001, /* GPIO1 == ADCLRCLK1 */ - 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */ - 0x0141, /* GPIO3 == HP_SEL */ - 0x0002, /* GPIO4 == IRQ */ - 0x020e, /* GPIO5 == CLKOUT */ - }, - - .retune_mobile_cfgs = wm8996_retune, - .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune), -}; - -static struct wm8962_pdata wm8962_pdata __initdata = { - .gpio_init = { - 0, - WM8962_GPIO_FN_OPCLK, - WM8962_GPIO_FN_DMICCLK, - 0, - 0x8000 | WM8962_GPIO_FN_DMICDAT, - WM8962_GPIO_FN_IRQ, /* Open drain mode */ - }, - .irq_active_low = true, -}; - -static struct wm9081_pdata wm9081_pdata __initdata = { - .irq_high = false, - .irq_cmos = false, -}; - static struct i2c_board_info i2c_devs1[] __initdata = { { I2C_BOARD_INFO("wm8311", 0x34), .irq = S3C_EINT(0), .platform_data = &glenfarclas_pmic_pdata }, + { I2C_BOARD_INFO("wlf-gf-module", 0x24) }, + { I2C_BOARD_INFO("wlf-gf-module", 0x25) }, + { I2C_BOARD_INFO("wlf-gf-module", 0x26) }, + { I2C_BOARD_INFO("wm1250-ev1", 0x27) }, - { I2C_BOARD_INFO("wm8996", 0x1a), - .platform_data = &wm8996_pdata, - .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, - }, - { I2C_BOARD_INFO("wm9081", 0x6c), - .platform_data = &wm9081_pdata, }, - { I2C_BOARD_INFO("wm8962", 0x1a), - .platform_data = &wm8962_pdata, - .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, - }, }; static void __init crag6410_map_io(void) diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c index 19a0887e1c1e..952f75ff5deb 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c64xx/mach-hmt.c @@ -37,7 +37,7 @@ #include <plat/fb.h> #include <plat/nand.h> -#include <mach/s3c6410.h> +#include <plat/s3c6410.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c index fb8969aa412e..1bc85c359498 100644 --- a/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/arch/arm/mach-s3c64xx/mach-mini6410.c @@ -32,8 +32,8 @@ #include <mach/regs-gpio.h> #include <mach/regs-modem.h> #include <mach/regs-srom.h> -#include <mach/s3c6410.h> +#include <plat/s3c6410.h> #include <plat/adc.h> #include <plat/cpu.h> #include <plat/devs.h> diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c index c30f2e5e0d85..cb13cba98b3d 100644 --- a/arch/arm/mach-s3c64xx/mach-ncp.c +++ b/arch/arm/mach-s3c64xx/mach-ncp.c @@ -39,7 +39,7 @@ #include <plat/iic.h> #include <plat/fb.h> -#include <mach/s3c6410.h> +#include <plat/s3c6410.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c index 93170d4834e7..87281e4b8471 100644 --- a/arch/arm/mach-s3c64xx/mach-real6410.c +++ b/arch/arm/mach-s3c64xx/mach-real6410.c @@ -33,8 +33,8 @@ #include <mach/regs-gpio.h> #include <mach/regs-modem.h> #include <mach/regs-srom.h> -#include <mach/s3c6410.h> +#include <plat/s3c6410.h> #include <plat/adc.h> #include <plat/cpu.h> #include <plat/devs.h> diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c index cbb57ded3d95..94c831d88365 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq5.c +++ b/arch/arm/mach-s3c64xx/mach-smartq5.c @@ -22,8 +22,8 @@ #include <mach/map.h> #include <mach/regs-gpio.h> -#include <mach/s3c6410.h> +#include <plat/s3c6410.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/fb.h> diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c index 04f914b85fdf..f112547ce80a 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq7.c +++ b/arch/arm/mach-s3c64xx/mach-smartq7.c @@ -22,8 +22,8 @@ #include <mach/map.h> #include <mach/regs-gpio.h> -#include <mach/s3c6410.h> +#include <plat/s3c6410.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/fb.h> diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c index 6fd5e95f8f75..73450c2b530a 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6400.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c @@ -31,7 +31,7 @@ #include <plat/regs-serial.h> -#include <mach/s3c6400.h> +#include <plat/s3c6400.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 5f147c33edad..8bc8edd85e5a 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c @@ -63,7 +63,7 @@ #include <plat/fb.h> #include <plat/gpio-cfg.h> -#include <mach/s3c6410.h> +#include <plat/s3c6410.h> #include <plat/clock.h> #include <plat/devs.h> #include <plat/cpu.h> diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c index 055e2858b0dd..b375cd5c47cb 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c64xx/pm.c @@ -29,6 +29,7 @@ #include <mach/regs-clock.h> #include <mach/regs-syscon-power.h> #include <mach/regs-gpio-memport.h> +#include <mach/regs-modem.h> #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK void s3c_pm_debug_smdkled(u32 set, u32 clear) @@ -85,6 +86,9 @@ static struct sleep_save misc_save[] = { SAVE_ITEM(S3C64XX_MEM0CONSLP0), SAVE_ITEM(S3C64XX_MEM0CONSLP1), SAVE_ITEM(S3C64XX_MEM1CONSLP), + + SAVE_ITEM(S3C64XX_SDMA_SEL), + SAVE_ITEM(S3C64XX_MODEM_MIFPCON), }; void s3c_pm_configure_extint(void) diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index 5e93fe3f3f40..7a3bc32df425 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c @@ -38,7 +38,7 @@ #include <plat/sdhci.h> #include <plat/iic-core.h> #include <plat/onenand-core.h> -#include <mach/s3c6400.h> +#include <plat/s3c6400.h> void __init s3c6400_map_io(void) { diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index 312aa6b115e8..4117003464ad 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c @@ -41,8 +41,8 @@ #include <plat/adc-core.h> #include <plat/iic-core.h> #include <plat/onenand-core.h> -#include <mach/s3c6400.h> -#include <mach/s3c6410.h> +#include <plat/s3c6400.h> +#include <plat/s3c6410.h> void __init s3c6410_map_io(void) { diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c index f344a222bc84..c75a71b21165 100644 --- a/arch/arm/mach-s3c64xx/setup-sdhci.c +++ b/arch/arm/mach-s3c64xx/setup-sdhci.c @@ -12,17 +12,7 @@ * published by the Free Software Foundation. */ -#include <linux/kernel.h> #include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <linux/mmc/card.h> -#include <linux/mmc/host.h> - -#include <plat/regs-sdhci.h> -#include <plat/sdhci.h> /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ @@ -32,41 +22,3 @@ char *s3c64xx_hsmmc_clksrcs[4] = { [2] = "mmc_bus", /* [3] = "48m", - note not successfully used yet */ }; - -void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card) -{ - u32 ctrl2, ctrl3; - - ctrl2 = readl(r + S3C_SDHCI_CONTROL2); - ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; - ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | - S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | - S3C_SDHCI_CTRL2_DFCNT_NONE | - S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); - - pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3); - writel(ctrl2, r + S3C_SDHCI_CONTROL2); - writel(ctrl3, r + S3C_SDHCI_CONTROL3); -} - -void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card) -{ - writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); - - s3c6400_setup_sdhci_cfg_card(dev, r, ios, card); -} diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig index 9527ed24dbff..18690c5f99e6 100644 --- a/arch/arm/mach-s5p64x0/Kconfig +++ b/arch/arm/mach-s5p64x0/Kconfig @@ -11,6 +11,8 @@ config CPU_S5P6440 bool select SAMSUNG_DMADEV select S5P_HRT + select S5P_SLEEP if PM + select SAMSUNG_WAKEMASK if PM help Enable S5P6440 CPU support @@ -18,9 +20,17 @@ config CPU_S5P6450 bool select SAMSUNG_DMADEV select S5P_HRT + select S5P_SLEEP if PM + select SAMSUNG_WAKEMASK if PM help Enable S5P6450 CPU support +config S5P64X0_SETUP_FB_24BPP + bool + help + Common setup code for S5P64X0 based boards with a LCD display + through RGB interface. + config S5P64X0_SETUP_I2C1 bool help @@ -31,6 +41,7 @@ config S5P64X0_SETUP_I2C1 config MACH_SMDK6440 bool "SMDK6440" select CPU_S5P6440 + select S3C_DEV_FB select S3C_DEV_I2C1 select S3C_DEV_RTC select S3C_DEV_WDT @@ -39,6 +50,7 @@ config MACH_SMDK6440 select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_PWM select SAMSUNG_DEV_TS + select S5P64X0_SETUP_FB_24BPP select S5P64X0_SETUP_I2C1 help Machine support for the Samsung SMDK6440 @@ -46,6 +58,7 @@ config MACH_SMDK6440 config MACH_SMDK6450 bool "SMDK6450" select CPU_S5P6450 + select S3C_DEV_FB select S3C_DEV_I2C1 select S3C_DEV_RTC select S3C_DEV_WDT @@ -54,6 +67,7 @@ config MACH_SMDK6450 select SAMSUNG_DEV_BACKLIGHT select SAMSUNG_DEV_PWM select SAMSUNG_DEV_TS + select S5P64X0_SETUP_FB_24BPP select S5P64X0_SETUP_I2C1 help Machine support for the Samsung SMDK6450 diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile index 5f6afdf067ed..a1324d8dc4e0 100644 --- a/arch/arm/mach-s5p64x0/Makefile +++ b/arch/arm/mach-s5p64x0/Makefile @@ -12,10 +12,11 @@ obj- := # Core support for S5P64X0 system -obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o +obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o +obj-$(CONFIG_PM) += pm.o irq-pm.o # machine support @@ -28,3 +29,4 @@ obj-y += dev-audio.o obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o +obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index c1f548f69a0d..c54c65d511f0 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c @@ -147,6 +147,7 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 8), }, { .name = "dma", + .devname = "dma-pl330", .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 12), diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index 3d9b60975570..2d04abfba12e 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c @@ -180,6 +180,7 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 3), }, { .name = "dma", + .devname = "dma-pl330", .parent = &clk_hclk_low.clk, .enable = s5p64x0_hclk0_ctrl, .ctrlbit = (1 << 12), diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c index 8a938542c54d..ecab40cf19ab 100644 --- a/arch/arm/mach-s5p64x0/cpu.c +++ b/arch/arm/mach-s5p64x0/cpu.c @@ -39,6 +39,7 @@ #include <plat/s5p6440.h> #include <plat/s5p6450.h> #include <plat/adc-core.h> +#include <plat/fb-core.h> /* Initial IO mappings */ @@ -109,6 +110,7 @@ void __init s5p6440_map_io(void) { /* initialize any device information early */ s3c_adc_setname("s3c64xx-adc"); + s3c_fb_setname("s5p64x0-fb"); iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc)); @@ -119,6 +121,7 @@ void __init s5p6450_map_io(void) { /* initialize any device information early */ s3c_adc_setname("s3c64xx-adc"); + s3c_fb_setname("s5p64x0-fb"); iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h b/arch/arm/mach-s5p64x0/include/mach/clkdev.h deleted file mode 100644 index 7dffa83d23ff..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_CLKDEV_H__ -#define __MACH_CLKDEV_H__ - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do {} while (0) - -#endif diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h index 5837a36ece8d..53982db9d259 100644 --- a/arch/arm/mach-s5p64x0/include/mach/irqs.h +++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h @@ -87,6 +87,10 @@ #define IRQ_I2S0 IRQ_I2SV40 +#define IRQ_LCD_FIFO IRQ_DISPCON0 +#define IRQ_LCD_VSYNC IRQ_DISPCON1 +#define IRQ_LCD_SYSTEM IRQ_DISPCON2 + /* S5P6450 EINT feature will be added */ /* diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h index 95c91257c7ca..4d3ac8a3709d 100644 --- a/arch/arm/mach-s5p64x0/include/mach/map.h +++ b/arch/arm/mach-s5p64x0/include/mach/map.h @@ -47,6 +47,8 @@ #define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) +#define S5P64X0_PA_FB 0xEE000000 + #define S5P64X0_PA_I2S 0xF2000000 #define S5P6450_PA_I2S1 0xF2800000 #define S5P6450_PA_I2S2 0xF2900000 @@ -64,6 +66,7 @@ #define S3C_PA_IIC1 S5P6440_PA_IIC1 #define S3C_PA_RTC S5P64X0_PA_RTC #define S3C_PA_WDT S5P64X0_PA_WDT +#define S3C_PA_FB S5P64X0_PA_FB #define S5P_PA_CHIPID S5P64X0_PA_CHIPID #define S5P_PA_SROMC S5P64X0_PA_SROMC @@ -85,5 +88,6 @@ #define S5P_PA_UART5 S5P6450_PA_UART(5) #define S5P_SZ_UART SZ_256 +#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h new file mode 100644 index 000000000000..e52f7545d3aa --- /dev/null +++ b/arch/arm/mach-s5p64x0/include/mach/pm-core.h @@ -0,0 +1,117 @@ +/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c + * + * Based on PM core support for S3C64XX by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <mach/regs-gpio.h> + +static inline void s3c_pm_debug_init_uart(void) +{ + u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK); + + /* + * As a note, since the S5P64X0 UARTs generally have multiple + * clock sources, we simply enable PCLK at the moment and hope + * that the resume settings for the UART are suitable for the + * use with PCLK. + */ + tmp |= S5P64X0_CLK_GATE_PCLK_UART0; + tmp |= S5P64X0_CLK_GATE_PCLK_UART1; + tmp |= S5P64X0_CLK_GATE_PCLK_UART2; + tmp |= S5P64X0_CLK_GATE_PCLK_UART3; + + __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK); + udelay(10); +} + +static inline void s3c_pm_arch_prepare_irqs(void) +{ + /* VIC should have already been taken care of */ + + /* clear any pending EINT0 interrupts */ + __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND); +} + +static inline void s3c_pm_arch_stop_clocks(void) { } +static inline void s3c_pm_arch_show_resume_irqs(void) { } + +/* + * make these defines, we currently do not have any need to change + * the IRQ wake controls depending on the CPU we are running on + */ +#define s3c_irqwake_eintallow ((1 << 16) - 1) +#define s3c_irqwake_intallow (~0) + +static inline void s3c_pm_arch_update_uart(void __iomem *regs, + struct pm_uart_save *save) +{ + u32 ucon = __raw_readl(regs + S3C2410_UCON); + u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; + u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; + u32 new_ucon; + u32 delta; + + /* + * S5P64X0 UART blocks only support level interrupts, so ensure that + * when we restore unused UART blocks we force the level interrupt + * settings. + */ + save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; + + /* + * We have a constraint on changing the clock type of the UART + * between UCLKx and PCLK, so ensure that when we restore UCON + * that the CLK field is correctly modified if the bootloader + * has changed anything. + */ + if (ucon_clk != save_clk) { + new_ucon = save->ucon; + delta = ucon_clk ^ save_clk; + + /* + * change from UCLKx => wrong PCLK, + * either UCLK can be tested for by a bit-test + * with UCLK0 + */ + if (ucon_clk & S3C6400_UCON_UCLK0 && + !(save_clk & S3C6400_UCON_UCLK0) && + delta & S3C6400_UCON_PCLK2) { + new_ucon &= ~S3C6400_UCON_UCLK0; + } else if (delta == S3C6400_UCON_PCLK2) { + /* + * as a precaution, don't change from + * PCLK2 => PCLK or vice-versa + */ + new_ucon ^= S3C6400_UCON_PCLK2; + } + + S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", + ucon, new_ucon, save->ucon); + save->ucon = new_ucon; + } +} + +static inline void s3c_pm_restored_gpios(void) +{ + /* ensure sleep mode has been cleared from the system */ + __raw_writel(0, S5P64X0_SLPEN); +} + +static inline void samsung_pm_saved_gpios(void) +{ + /* + * turn on the sleep mode and keep it there, as it seems that during + * suspend the xCON registers get re-set and thus you can end up with + * problems between going to sleep and resuming. + */ + __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN); +} diff --git a/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h deleted file mode 100644 index 19fff8b701c0..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h +++ /dev/null @@ -1,68 +0,0 @@ -/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h - * - * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S5P64X0 - pwm clock and timer support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_PWMCLK_H -#define __ASM_ARCH_PWMCLK_H __FILE__ - -/** - * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @tcfg: The timer TCFG1 register bits shifted down to 0. - * - * Return true if the given configuration from TCFG1 is a TCLK instead - * any of the TDIV clocks. - */ -static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) -{ - return 0; -} - -/** - * tcfg_to_divisor() - convert tcfg1 setting to a divisor - * @tcfg1: The tcfg1 setting, shifted down. - * - * Get the divisor value for the given tcfg1 setting. We assume the - * caller has already checked to see if this is not a TCLK source. - */ -static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) -{ - return 1 << tcfg1; -} - -/** - * pwm_tdiv_has_div1() - does the tdiv setting have a /1 - * - * Return true if we have a /1 in the tdiv setting. - */ -static inline unsigned int pwm_tdiv_has_div1(void) -{ - return 1; -} - -/** - * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. - * @div: The divisor to calculate the bit information for. - * - * Turn a divisor into the necessary bit field for TCFG1. - */ -static inline unsigned long pwm_tdiv_div_bits(unsigned int div) -{ - return ilog2(div); -} - -#define S3C_TCFG1_MUX_TCLK 0 - -#endif /* __ASM_ARCH_PWMCLK_H */ diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h index a133f22fa155..bd91112c813c 100644 --- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h +++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h @@ -41,17 +41,50 @@ #define S5P6450_DPLL_CON S5P_CLKREG(0x50) #define S5P6450_DPLL_CON_K S5P_CLKREG(0x54) +#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100) #define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C) #define S5P64X0_SYS_ID S5P_CLKREG(0x118) #define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C) #define S5P64X0_PWR_CFG S5P_CLKREG(0x804) +#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808) +#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818) +#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828) + #define S5P64X0_OTHERS S5P_CLKREG(0x900) +#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908) + +#define S5P64X0_INFORM0 S5P_CLKREG(0xA00) #define S5P64X0_CLKDIV0_HCLK_SHIFT (8) #define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT) +/* HCLK GATE Registers */ +#define S5P64X0_CLK_GATE_HCLK1_FIMGVG (1 << 2) +#define S5P64X0_CLK_GATE_SCLK1_FIMGVG (1 << 2) + +/* PCLK GATE Registers */ +#define S5P64X0_CLK_GATE_PCLK_UART3 (1 << 4) +#define S5P64X0_CLK_GATE_PCLK_UART2 (1 << 3) +#define S5P64X0_CLK_GATE_PCLK_UART1 (1 << 2) +#define S5P64X0_CLK_GATE_PCLK_UART0 (1 << 1) + +#define S5P64X0_PWR_CFG_MMC1_DISABLE (1 << 15) +#define S5P64X0_PWR_CFG_MMC0_DISABLE (1 << 14) +#define S5P64X0_PWR_CFG_RTC_TICK_DISABLE (1 << 11) +#define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE (1 << 10) +#define S5P64X0_PWR_CFG_WFI_MASK (3 << 5) +#define S5P64X0_PWR_CFG_WFI_SLEEP (3 << 5) + +#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0) + +#define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0) + +#define S5P6450_OTHERS_DISABLE_INT (1 << 31) +#define S5P64X0_OTHERS_RET_UART (1 << 26) +#define S5P64X0_OTHERS_RET_MMC1 (1 << 25) +#define S5P64X0_OTHERS_RET_MMC0 (1 << 24) #define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16) /* Compatibility defines */ diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h index 6ce254729f3b..cfdfa4fdadf2 100644 --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h @@ -34,14 +34,35 @@ #define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) #define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) +#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0) +#define S5P64X0_SPCON0_LCD_SEL_MASK (0x3 << 0) +#define S5P64X0_SPCON0_LCD_SEL_RGB (0x1 << 0) +#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0) + +#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0) +#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4) +#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0) +#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4) + +#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200) +#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220) +#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240) + /* External interrupt control registers for group0 */ #define EINT0CON0_OFFSET (0x900) +#define EINT0FLTCON0_OFFSET (0x910) +#define EINT0FLTCON1_OFFSET (0x914) #define EINT0MASK_OFFSET (0x920) #define EINT0PEND_OFFSET (0x924) #define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET) +#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO + EINT0FLTCON0_OFFSET) +#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO + EINT0FLTCON1_OFFSET) #define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET) #define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET) +#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930) +#define S5P64X0_SLPEN_USE_xSLP (1 << 0) + #endif /* __ASM_ARCH_REGS_GPIO_H */ diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c index 494e1a8f6f6d..275dc74f4a7b 100644 --- a/arch/arm/mach-s5p64x0/irq-eint.c +++ b/arch/arm/mach-s5p64x0/irq-eint.c @@ -20,6 +20,7 @@ #include <plat/cpu.h> #include <plat/regs-irqtype.h> #include <plat/gpio-cfg.h> +#include <plat/pm.h> #include <mach/regs-gpio.h> #include <mach/regs-clock.h> @@ -134,6 +135,7 @@ static int s5p64x0_alloc_gc(void) ct->chip.irq_mask = irq_gc_mask_set_bit; ct->chip.irq_unmask = irq_gc_mask_clr_bit; ct->chip.irq_set_type = s5p64x0_irq_eint_set_type; + ct->chip.irq_set_wake = s3c_irqext_wake; ct->regs.ack = EINT0PEND_OFFSET; ct->regs.mask = EINT0MASK_OFFSET; irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE, diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c new file mode 100644 index 000000000000..3e6f2456ee9d --- /dev/null +++ b/arch/arm/mach-s5p64x0/irq-pm.c @@ -0,0 +1,92 @@ +/* linux/arch/arm/mach-s5p64x0/irq-pm.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P64X0 - Interrupt handling Power Management + * + * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/syscore_ops.h> +#include <linux/serial_core.h> +#include <linux/io.h> + +#include <plat/regs-serial.h> +#include <plat/pm.h> + +#include <mach/regs-gpio.h> + +static struct sleep_save irq_save[] = { + SAVE_ITEM(S5P64X0_EINT0CON0), + SAVE_ITEM(S5P64X0_EINT0FLTCON0), + SAVE_ITEM(S5P64X0_EINT0FLTCON1), + SAVE_ITEM(S5P64X0_EINT0MASK), +}; + +static struct irq_grp_save { + u32 con; + u32 fltcon; + u32 mask; +} eint_grp_save[4]; + +static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS]; + +static int s5p64x0_irq_pm_suspend(void) +{ + struct irq_grp_save *grp = eint_grp_save; + int i; + + S3C_PMDBG("%s: suspending IRQs\n", __func__); + + s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); + + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) + irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM); + + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { + grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4)); + grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4)); + grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4)); + } + + return 0; +} + +static void s5p64x0_irq_pm_resume(void) +{ + struct irq_grp_save *grp = eint_grp_save; + int i; + + S3C_PMDBG("%s: resuming IRQs\n", __func__); + + s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); + + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) + __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM); + + for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { + __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4)); + __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4)); + __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4)); + } + + S3C_PMDBG("%s: IRQ configuration restored\n", __func__); +} + +static struct syscore_ops s5p64x0_irq_syscore_ops = { + .suspend = s5p64x0_irq_pm_suspend, + .resume = s5p64x0_irq_pm_resume, +}; + +static int __init s5p64x0_syscore_init(void) +{ + register_syscore_ops(&s5p64x0_irq_syscore_ops); + + return 0; +} +core_initcall(s5p64x0_syscore_init); diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c index 88857f5a49f7..4a1250cd1356 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c @@ -23,6 +23,9 @@ #include <linux/clk.h> #include <linux/gpio.h> #include <linux/pwm_backlight.h> +#include <linux/fb.h> + +#include <video/platform_lcd.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -47,6 +50,8 @@ #include <plat/ts.h> #include <plat/s5p-time.h> #include <plat/backlight.h> +#include <plat/fb.h> +#include <plat/regs-fb.h> #define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ @@ -92,6 +97,59 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { }, }; +/* Frame Buffer */ +static struct s3c_fb_pd_win smdk6440_fb_win0 = { + .win_mode = { + .left_margin = 8, + .right_margin = 13, + .upper_margin = 7, + .lower_margin = 5, + .hsync_len = 3, + .vsync_len = 1, + .xres = 800, + .yres = 480, + }, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = { + .win[0] = &smdk6440_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .setup_gpio = s5p64x0_fb_gpio_setup_24bpp, +}; + +/* LCD power controller */ +static void smdk6440_lte480_reset_power(struct plat_lcd_data *pd, + unsigned int power) +{ + int err; + + if (power) { + err = gpio_request(S5P6440_GPN(5), "GPN"); + if (err) { + printk(KERN_ERR "failed to request GPN for lcd reset\n"); + return; + } + + gpio_direction_output(S5P6440_GPN(5), 1); + gpio_set_value(S5P6440_GPN(5), 0); + gpio_set_value(S5P6440_GPN(5), 1); + gpio_free(S5P6440_GPN(5)); + } +} + +static struct plat_lcd_data smdk6440_lcd_power_data = { + .set_power = smdk6440_lte480_reset_power, +}; + +static struct platform_device smdk6440_lcd_lte480wv = { + .name = "platform-lcd", + .dev.parent = &s3c_device_fb.dev, + .dev.platform_data = &smdk6440_lcd_power_data, +}; + static struct platform_device *smdk6440_devices[] __initdata = { &s3c_device_adc, &s3c_device_rtc, @@ -101,6 +159,8 @@ static struct platform_device *smdk6440_devices[] __initdata = { &s3c_device_wdt, &samsung_asoc_dma, &s5p6440_device_iis, + &s3c_device_fb, + &smdk6440_lcd_lte480wv, }; static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = { @@ -147,6 +207,17 @@ static void __init smdk6440_map_io(void) s5p_set_timer_source(S5P_PWM3, S5P_PWM4); } +static void s5p6440_set_lcd_interface(void) +{ + unsigned int cfg; + + /* select TFT LCD type (RGB I/F) */ + cfg = __raw_readl(S5P64X0_SPCON0); + cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK; + cfg |= S5P64X0_SPCON0_LCD_SEL_RGB; + __raw_writel(cfg, S5P64X0_SPCON0); +} + static void __init smdk6440_machine_init(void) { s3c24xx_ts_set_platdata(NULL); @@ -160,6 +231,9 @@ static void __init smdk6440_machine_init(void) samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data); + s5p6440_set_lcd_interface(); + s3c_fb_set_platdata(&smdk6440_lcd_pdata); + platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); } diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c index e1b277b94610..0ab129ecf009 100644 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c @@ -23,6 +23,9 @@ #include <linux/clk.h> #include <linux/gpio.h> #include <linux/pwm_backlight.h> +#include <linux/fb.h> + +#include <video/platform_lcd.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -47,6 +50,8 @@ #include <plat/ts.h> #include <plat/s5p-time.h> #include <plat/backlight.h> +#include <plat/fb.h> +#include <plat/regs-fb.h> #define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ @@ -110,6 +115,59 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = { #endif }; +/* Frame Buffer */ +static struct s3c_fb_pd_win smdk6450_fb_win0 = { + .win_mode = { + .left_margin = 8, + .right_margin = 13, + .upper_margin = 7, + .lower_margin = 5, + .hsync_len = 3, + .vsync_len = 1, + .xres = 800, + .yres = 480, + }, + .max_bpp = 32, + .default_bpp = 24, +}; + +static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = { + .win[0] = &smdk6450_fb_win0, + .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, + .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, + .setup_gpio = s5p64x0_fb_gpio_setup_24bpp, +}; + +/* LCD power controller */ +static void smdk6450_lte480_reset_power(struct plat_lcd_data *pd, + unsigned int power) +{ + int err; + + if (power) { + err = gpio_request(S5P6450_GPN(5), "GPN"); + if (err) { + printk(KERN_ERR "failed to request GPN for lcd reset\n"); + return; + } + + gpio_direction_output(S5P6450_GPN(5), 1); + gpio_set_value(S5P6450_GPN(5), 0); + gpio_set_value(S5P6450_GPN(5), 1); + gpio_free(S5P6450_GPN(5)); + } +} + +static struct plat_lcd_data smdk6450_lcd_power_data = { + .set_power = smdk6450_lte480_reset_power, +}; + +static struct platform_device smdk6450_lcd_lte480wv = { + .name = "platform-lcd", + .dev.parent = &s3c_device_fb.dev, + .dev.platform_data = &smdk6450_lcd_power_data, +}; + static struct platform_device *smdk6450_devices[] __initdata = { &s3c_device_adc, &s3c_device_rtc, @@ -119,6 +177,9 @@ static struct platform_device *smdk6450_devices[] __initdata = { &s3c_device_wdt, &samsung_asoc_dma, &s5p6450_device_iis0, + &s3c_device_fb, + &smdk6450_lcd_lte480wv, + /* s5p6450_device_spi0 will be added */ }; @@ -166,6 +227,17 @@ static void __init smdk6450_map_io(void) s5p_set_timer_source(S5P_PWM3, S5P_PWM4); } +static void s5p6450_set_lcd_interface(void) +{ + unsigned int cfg; + + /* select TFT LCD type (RGB I/F) */ + cfg = __raw_readl(S5P64X0_SPCON0); + cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK; + cfg |= S5P64X0_SPCON0_LCD_SEL_RGB; + __raw_writel(cfg, S5P64X0_SPCON0); +} + static void __init smdk6450_machine_init(void) { s3c24xx_ts_set_platdata(NULL); @@ -179,6 +251,9 @@ static void __init smdk6450_machine_init(void) samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data); + s5p6450_set_lcd_interface(); + s3c_fb_set_platdata(&smdk6450_lcd_pdata); + platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices)); } diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c new file mode 100644 index 000000000000..69927243d25f --- /dev/null +++ b/arch/arm/mach-s5p64x0/pm.c @@ -0,0 +1,204 @@ +/* linux/arch/arm/mach-s5p64x0/pm.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P64X0 Power Management Support + * + * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/suspend.h> +#include <linux/syscore_ops.h> +#include <linux/io.h> + +#include <plat/cpu.h> +#include <plat/pm.h> +#include <plat/regs-timer.h> +#include <plat/wakeup-mask.h> + +#include <mach/regs-clock.h> +#include <mach/regs-gpio.h> + +static struct sleep_save s5p64x0_core_save[] = { + SAVE_ITEM(S5P64X0_APLL_CON), + SAVE_ITEM(S5P64X0_MPLL_CON), + SAVE_ITEM(S5P64X0_EPLL_CON), + SAVE_ITEM(S5P64X0_EPLL_CON_K), + SAVE_ITEM(S5P64X0_CLK_SRC0), + SAVE_ITEM(S5P64X0_CLK_SRC1), + SAVE_ITEM(S5P64X0_CLK_DIV0), + SAVE_ITEM(S5P64X0_CLK_DIV1), + SAVE_ITEM(S5P64X0_CLK_DIV2), + SAVE_ITEM(S5P64X0_CLK_DIV3), + SAVE_ITEM(S5P64X0_CLK_GATE_MEM0), + SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1), + SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1), +}; + +static struct sleep_save s5p64x0_misc_save[] = { + SAVE_ITEM(S5P64X0_AHB_CON0), + SAVE_ITEM(S5P64X0_SPCON0), + SAVE_ITEM(S5P64X0_SPCON1), + SAVE_ITEM(S5P64X0_MEM0CONSLP0), + SAVE_ITEM(S5P64X0_MEM0CONSLP1), + SAVE_ITEM(S5P64X0_MEM0DRVCON), + SAVE_ITEM(S5P64X0_MEM1DRVCON), + + SAVE_ITEM(S3C64XX_TINT_CSTAT), +}; + +/* DPLL is present only in S5P6450 */ +static struct sleep_save s5p6450_core_save[] = { + SAVE_ITEM(S5P6450_DPLL_CON), + SAVE_ITEM(S5P6450_DPLL_CON_K), +}; + +void s3c_pm_configure_extint(void) +{ + __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK); +} + +void s3c_pm_restore_core(void) +{ + __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK); + + s3c_pm_do_restore_core(s5p64x0_core_save, + ARRAY_SIZE(s5p64x0_core_save)); + + if (soc_is_s5p6450()) + s3c_pm_do_restore_core(s5p6450_core_save, + ARRAY_SIZE(s5p6450_core_save)); + + s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save)); +} + +void s3c_pm_save_core(void) +{ + s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save)); + + if (soc_is_s5p6450()) + s3c_pm_do_save(s5p6450_core_save, + ARRAY_SIZE(s5p6450_core_save)); + + s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save)); +} + +static int s5p64x0_cpu_suspend(unsigned long arg) +{ + unsigned long tmp = 0; + + /* + * Issue the standby signal into the pm unit. Note, we + * issue a write-buffer drain just in case. + */ + asm("b 1f\n\t" + ".align 5\n\t" + "1:\n\t" + "mcr p15, 0, %0, c7, c10, 5\n\t" + "mcr p15, 0, %0, c7, c10, 4\n\t" + "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp)); + + /* we should never get past here */ + panic("sleep resumed to originator?"); +} + +/* mapping of interrupts to parts of the wakeup mask */ +static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = { + { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, }, + { .irq = IRQ_RTC_TIC, .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, }, + { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, }, + { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, }, +}; + +static void s5p64x0_pm_prepare(void) +{ + u32 tmp; + + samsung_sync_wakemask(S5P64X0_PWR_CFG, + s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs)); + + /* store the resume address in INFORM0 register */ + __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0); + + /* setup clock gating for FIMGVG block */ + __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \ + (S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1); + __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \ + (S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1); + + /* Configure the stabilization counter with wait time required */ + __raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE); + + /* set WFI to SLEEP mode configuration */ + tmp = __raw_readl(S5P64X0_SLEEP_CFG); + tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN); + __raw_writel(tmp, S5P64X0_SLEEP_CFG); + + tmp = __raw_readl(S5P64X0_PWR_CFG); + tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK); + tmp |= S5P64X0_PWR_CFG_WFI_SLEEP; + __raw_writel(tmp, S5P64X0_PWR_CFG); + + /* + * set OTHERS register to disable interrupt before going to + * sleep. This bit is present only in S5P6450, it is reserved + * in S5P6440. + */ + if (soc_is_s5p6450()) { + tmp = __raw_readl(S5P64X0_OTHERS); + tmp |= S5P6450_OTHERS_DISABLE_INT; + __raw_writel(tmp, S5P64X0_OTHERS); + } + + /* ensure previous wakeup state is cleared before sleeping */ + __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT); + +} + +static int s5p64x0_pm_add(struct sys_device *sysdev) +{ + pm_cpu_prep = s5p64x0_pm_prepare; + pm_cpu_sleep = s5p64x0_cpu_suspend; + pm_uart_udivslot = 1; + + return 0; +} + +static struct sysdev_driver s5p64x0_pm_driver = { + .add = s5p64x0_pm_add, +}; + +static __init int s5p64x0_pm_drvinit(void) +{ + s3c_pm_init(); + + return sysdev_driver_register(&s5p64x0_sysclass, &s5p64x0_pm_driver); +} +arch_initcall(s5p64x0_pm_drvinit); + +static void s5p64x0_pm_resume(void) +{ + u32 tmp; + + tmp = __raw_readl(S5P64X0_OTHERS); + tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \ + S5P64X0_OTHERS_RET_UART); + __raw_writel(tmp , S5P64X0_OTHERS); +} + +static struct syscore_ops s5p64x0_pm_syscore_ops = { + .resume = s5p64x0_pm_resume, +}; + +static __init int s5p64x0_pm_syscore_init(void) +{ + register_syscore_ops(&s5p64x0_pm_syscore_ops); + + return 0; +} +arch_initcall(s5p64x0_pm_syscore_init); diff --git a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c new file mode 100644 index 000000000000..f346ee4af54d --- /dev/null +++ b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c @@ -0,0 +1,29 @@ +/* linux/arch/arm/mach-s5p64x0/setup-fb-24bpp.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base S5P64X0 GPIO setup information for LCD framebuffer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/fb.h> +#include <linux/gpio.h> + +#include <plat/cpu.h> +#include <plat/fb.h> +#include <plat/gpio-cfg.h> + +void s5p64x0_fb_gpio_setup_24bpp(void) +{ + if (soc_is_s5p6440()) { + s3c_gpio_cfgrange_nopull(S5P6440_GPI(0), 16, S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(S5P6440_GPJ(0), 12, S3C_GPIO_SFN(2)); + } else if (soc_is_s5p6450()) { + s3c_gpio_cfgrange_nopull(S5P6450_GPI(0), 16, S3C_GPIO_SFN(2)); + s3c_gpio_cfgrange_nopull(S5P6450_GPJ(0), 12, S3C_GPIO_SFN(2)); + } +} diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 6527c05c5fa1..8d47709da713 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c @@ -460,13 +460,13 @@ static struct clk init_clocks_off[] = { .ctrlbit = (1 << 2), }, { .name = "dma", - .devname = "s3c-pl330.1", + .devname = "dma-pl330.1", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 1), }, { .name = "dma", - .devname = "s3c-pl330.0", + .devname = "dma-pl330.0", .parent = &clk_div_d1_bus.clk, .enable = s5pc100_d1_0_ctrl, .ctrlbit = (1 << 0), diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c index ef803e92d35d..065a087f5a8b 100644 --- a/arch/arm/mach-s5pc100/dma.c +++ b/arch/arm/mach-s5pc100/dma.c @@ -260,6 +260,7 @@ struct amba_device s5pc100_device_pdma1 = { static int __init s5pc100_dma_init(void) { amba_device_register(&s5pc100_device_pdma0, &iomem_resource); + amba_device_register(&s5pc100_device_pdma1, &iomem_resource); return 0; } diff --git a/arch/arm/mach-s5pc100/include/mach/clkdev.h b/arch/arm/mach-s5pc100/include/mach/clkdev.h deleted file mode 100644 index 7dffa83d23ff..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_CLKDEV_H__ -#define __MACH_CLKDEV_H__ - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do {} while (0) - -#endif diff --git a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h deleted file mode 100644 index b34d2f7aae52..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h +++ /dev/null @@ -1,56 +0,0 @@ -/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min <bhmin@samsung.com> - * - * S5PC100 - pwm clock and timer support - * - * Based on mach-s3c6400/include/mach/pwm-clock.h - */ - -/** - * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @tcfg: The timer TCFG1 register bits shifted down to 0. - * - * Return true if the given configuration from TCFG1 is a TCLK instead - * any of the TDIV clocks. - */ -static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) -{ - return tcfg >= S3C64XX_TCFG1_MUX_TCLK; -} - -/** - * tcfg_to_divisor() - convert tcfg1 setting to a divisor - * @tcfg1: The tcfg1 setting, shifted down. - * - * Get the divisor value for the given tcfg1 setting. We assume the - * caller has already checked to see if this is not a TCLK source. - */ -static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) -{ - return 1 << tcfg1; -} - -/** - * pwm_tdiv_has_div1() - does the tdiv setting have a /1 - * - * Return true if we have a /1 in the tdiv setting. - */ -static inline unsigned int pwm_tdiv_has_div1(void) -{ - return 1; -} - -/** - * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. - * @div: The divisor to calculate the bit information for. - * - * Turn a divisor into the necessary bit field for TCFG1. - */ -static inline unsigned long pwm_tdiv_div_bits(unsigned int div) -{ - return ilog2(div); -} - -#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c index be25879bb2ee..6418c6e8a7b7 100644 --- a/arch/arm/mach-s5pc100/setup-sdhci.c +++ b/arch/arm/mach-s5pc100/setup-sdhci.c @@ -11,17 +11,7 @@ * published by the Free Software Foundation. */ -#include <linux/kernel.h> #include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <linux/mmc/card.h> -#include <linux/mmc/host.h> - -#include <plat/regs-sdhci.h> -#include <plat/sdhci.h> /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ @@ -31,35 +21,3 @@ char *s5pc100_hsmmc_clksrcs[4] = { [2] = "sclk_mmc", /* mmc_bus */ /* [3] = "48m", - note not successfully used yet */ }; - - -void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card) -{ - u32 ctrl2, ctrl3; - - /* don't need to alter anything according to card-type */ - - writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); - - ctrl2 = readl(r + S3C_SDHCI_CONTROL2); - ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; - ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | - S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | - S3C_SDHCI_CTRL2_DFCNT_NONE | - S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); - - writel(ctrl2, r + S3C_SDHCI_CONTROL2); - writel(ctrl3, r + S3C_SDHCI_CONTROL3); -} diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index e3ebe96923c8..646057ab2e4c 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -14,6 +14,8 @@ config CPU_S5PV210 select SAMSUNG_DMADEV select S5P_EXT_INT select S5P_HRT + select S5P_PM if PM + select S5P_SLEEP if PM help Enable S5PV210 CPU support @@ -93,11 +95,13 @@ config MACH_GONI select S3C_DEV_USB_HSOTG select S5P_DEV_ONENAND select SAMSUNG_DEV_KEYPAD + select S5P_DEV_TV select S5PV210_SETUP_FB_24BPP select S5PV210_SETUP_I2C1 select S5PV210_SETUP_I2C2 select S5PV210_SETUP_KEYPAD select S5PV210_SETUP_SDHCI + select S5PV210_SETUP_FIMC help Machine support for Samsung GONI board S5PC110(MCP) is one of package option of S5PV210 diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index ef7e4668d670..009fbe53df96 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -14,7 +14,7 @@ obj- := obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o -obj-$(CONFIG_PM) += pm.o sleep.o +obj-$(CONFIG_PM) += pm.o # machine support diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 1ab34000cc7e..4c5ac7a69e9e 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -174,6 +174,16 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); } +static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); +} + +static int exynos4_clk_dac_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable); +} + static struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", .rate = 27000000, @@ -295,13 +305,13 @@ static struct clk_ops clk_fout_apll_ops = { static struct clk init_clocks_off[] = { { .name = "dma", - .devname = "s3c-pl330.0", + .devname = "dma-pl330.0", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 3), }, { .name = "dma", - .devname = "s3c-pl330.1", + .devname = "dma-pl330.1", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 4), @@ -335,6 +345,40 @@ static struct clk init_clocks_off[] = { .enable = s5pv210_clk_ip0_ctrl, .ctrlbit = (1 << 16), }, { + .name = "dac", + .devname = "s5p-sdo", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 10), + }, { + .name = "mixer", + .devname = "s5p-mixer", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 9), + }, { + .name = "vp", + .devname = "s5p-mixer", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 8), + }, { + .name = "hdmi", + .devname = "s5pv210-hdmi", + .parent = &clk_hclk_dsys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 11), + }, { + .name = "hdmiphy", + .devname = "s5pv210-hdmi", + .enable = exynos4_clk_hdmiphy_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "dacphy", + .devname = "s5p-sdo", + .enable = exynos4_clk_dac_ctrl, + .ctrlbit = (1 << 0), + }, { .name = "otg", .parent = &clk_hclk_psys.clk, .enable = s5pv210_clk_ip1_ctrl, @@ -412,6 +456,12 @@ static struct clk init_clocks_off[] = { .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1<<9), }, { + .name = "i2c", + .devname = "s3c2440-hdmiphy-i2c", + .parent = &clk_pclk_psys.clk, + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 11), + }, { .name = "spi", .devname = "s3c64xx-spi.0", .parent = &clk_pclk_psys.clk, @@ -599,6 +649,23 @@ static struct clksrc_sources clkset_sclk_mixer = { .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), }; +static struct clksrc_clk clk_sclk_mixer = { + .clk = { + .name = "sclk_mixer", + .enable = s5pv210_clk_mask0_ctrl, + .ctrlbit = (1 << 1), + }, + .sources = &clkset_sclk_mixer, + .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, +}; + +static struct clksrc_clk *sclk_tv[] = { + &clk_sclk_dac, + &clk_sclk_pixel, + &clk_sclk_hdmi, + &clk_sclk_mixer, +}; + static struct clk *clkset_sclk_audio0_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_pcmcdclk0, @@ -782,14 +849,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, }, { .clk = { - .name = "sclk_mixer", - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 1), - }, - .sources = &clkset_sclk_mixer, - .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, - }, { - .clk = { .name = "sclk_fimc", .devname = "s5pv210-fimc.0", .enable = s5pv210_clk_mask1_ctrl, @@ -978,9 +1037,6 @@ static struct clksrc_clk *sysclks[] = { &clk_pclk_psys, &clk_vpllsrc, &clk_sclk_vpll, - &clk_sclk_dac, - &clk_sclk_pixel, - &clk_sclk_hdmi, &clk_mout_dmc0, &clk_sclk_dmc0, &clk_sclk_audio0, @@ -1065,6 +1121,61 @@ static struct clk_ops s5pv210_epll_ops = { .get_rate = s5p_epll_get_rate, }; +static u32 vpll_div[][5] = { + { 54000000, 3, 53, 3, 0 }, + { 108000000, 3, 53, 2, 0 }, +}; + +static unsigned long s5pv210_vpll_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int vpll_con; + unsigned int i; + + /* Return if nothing changed */ + if (clk->rate == rate) + return 0; + + vpll_con = __raw_readl(S5P_VPLL_CON); + vpll_con &= ~(0x1 << 27 | \ + PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \ + PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \ + PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(vpll_div); i++) { + if (vpll_div[i][0] == rate) { + vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT; + vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT; + vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT; + vpll_con |= vpll_div[i][4] << 27; + break; + } + } + + if (i == ARRAY_SIZE(vpll_div)) { + printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n", + __func__); + return -EINVAL; + } + + __raw_writel(vpll_con, S5P_VPLL_CON); + + /* Wait for VPLL lock */ + while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT))) + continue; + + clk->rate = rate; + return 0; +} +static struct clk_ops s5pv210_vpll_ops = { + .get_rate = s5pv210_vpll_get_rate, + .set_rate = s5pv210_vpll_set_rate, +}; + void __init_or_cpufreq s5pv210_setup_clocks(void) { struct clk *xtal_clk; @@ -1113,6 +1224,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) clk_fout_apll.ops = &clk_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; + clk_fout_vpll.ops = &s5pv210_vpll_ops; clk_fout_vpll.rate = vpll; printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", @@ -1158,6 +1270,9 @@ void __init s5pv210_register_clocks(void) for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) s3c_register_clksrc(sysclks[ptr], 1); + for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++) + s3c_register_clksrc(sclk_tv[ptr], 1); + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 91145720822c..84ec74633232 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -42,6 +42,7 @@ #include <plat/keypad-core.h> #include <plat/sdhci.h> #include <plat/reset.h> +#include <plat/tv-core.h> /* Initial IO mappings */ @@ -145,6 +146,9 @@ void __init s5pv210_map_io(void) /* Use s5pv210-keypad instead of samsung-keypad */ samsung_keypad_setname("s5pv210-keypad"); + + /* setup TV devices */ + s5p_hdmi_setname("s5pv210-hdmi"); } void __init s5pv210_init_clocks(int xtal) diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c index f79d0b06cbf9..86b749c18b77 100644 --- a/arch/arm/mach-s5pv210/dma.c +++ b/arch/arm/mach-s5pv210/dma.c @@ -254,6 +254,7 @@ struct amba_device s5pv210_device_pdma1 = { static int __init s5pv210_dma_init(void) { amba_device_register(&s5pv210_device_pdma0, &iomem_resource); + amba_device_register(&s5pv210_device_pdma1, &iomem_resource); return 0; } diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h deleted file mode 100644 index 7dffa83d23ff..000000000000 --- a/arch/arm/mach-s5pv210/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_CLKDEV_H__ -#define __MACH_CLKDEV_H__ - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do {} while (0) - -#endif diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index b9f9ec33384d..5e0de3a31f3d 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -56,7 +56,7 @@ #define IRQ_SPI2 S5P_IRQ_VIC1(17) #define IRQ_IRDA S5P_IRQ_VIC1(18) #define IRQ_IIC2 S5P_IRQ_VIC1(19) -#define IRQ_IIC3 S5P_IRQ_VIC1(20) +#define IRQ_IIC_HDMIPHY S5P_IRQ_VIC1(20) #define IRQ_HSIRX S5P_IRQ_VIC1(21) #define IRQ_HSITX S5P_IRQ_VIC1(22) #define IRQ_UHOST S5P_IRQ_VIC1(23) @@ -86,7 +86,7 @@ #define IRQ_HDMI S5P_IRQ_VIC2(12) #define IRQ_IIC1 S5P_IRQ_VIC2(13) #define IRQ_MFC S5P_IRQ_VIC2(14) -#define IRQ_TVENC S5P_IRQ_VIC2(15) +#define IRQ_SDO S5P_IRQ_VIC2(15) #define IRQ_I2S0 S5P_IRQ_VIC2(16) #define IRQ_I2S1 S5P_IRQ_VIC2(17) #define IRQ_I2S2 S5P_IRQ_VIC2(18) diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index aac343c180b2..7ff609f1568b 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -90,6 +90,12 @@ #define S5PV210_PA_FIMC1 0xFB300000 #define S5PV210_PA_FIMC2 0xFB400000 +#define S5PV210_PA_SDO 0xF9000000 +#define S5PV210_PA_VP 0xF9100000 +#define S5PV210_PA_MIXER 0xF9200000 +#define S5PV210_PA_HDMI 0xFA100000 +#define S5PV210_PA_IIC_HDMIPHY 0xFA900000 + /* Compatibiltiy Defines */ #define S3C_PA_FB S5PV210_PA_FB @@ -110,6 +116,13 @@ #define S5P_PA_FIMC2 S5PV210_PA_FIMC2 #define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS #define S5P_PA_MFC S5PV210_PA_MFC +#define S5P_PA_IIC_HDMIPHY S5PV210_PA_IIC_HDMIPHY + +#define S5P_PA_SDO S5PV210_PA_SDO +#define S5P_PA_VP S5PV210_PA_VP +#define S5P_PA_MIXER S5PV210_PA_MIXER +#define S5P_PA_HDMI S5PV210_PA_HDMI + #define S5P_PA_ONENAND S5PC110_PA_ONENAND #define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA #define S5P_PA_SDRAM S5PV210_PA_SDRAM diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h index 3e22109e1b7b..eba8aea63ed8 100644 --- a/arch/arm/mach-s5pv210/include/mach/pm-core.h +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h @@ -43,4 +43,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, } static inline void s3c_pm_restored_gpios(void) { } -static inline void s3c_pm_saved_gpios(void) { } +static inline void samsung_pm_saved_gpios(void) { } diff --git a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h deleted file mode 100644 index f8a9f1b330e0..000000000000 --- a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h +++ /dev/null @@ -1,70 +0,0 @@ -/* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h - * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h - * - * S5PV210 - pwm clock and timer support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_PWMCLK_H -#define __ASM_ARCH_PWMCLK_H __FILE__ - -/** - * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @tcfg: The timer TCFG1 register bits shifted down to 0. - * - * Return true if the given configuration from TCFG1 is a TCLK instead - * any of the TDIV clocks. - */ -static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) -{ - return tcfg == S3C64XX_TCFG1_MUX_TCLK; -} - -/** - * tcfg_to_divisor() - convert tcfg1 setting to a divisor - * @tcfg1: The tcfg1 setting, shifted down. - * - * Get the divisor value for the given tcfg1 setting. We assume the - * caller has already checked to see if this is not a TCLK source. - */ -static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) -{ - return 1 << tcfg1; -} - -/** - * pwm_tdiv_has_div1() - does the tdiv setting have a /1 - * - * Return true if we have a /1 in the tdiv setting. - */ -static inline unsigned int pwm_tdiv_has_div1(void) -{ - return 1; -} - -/** - * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. - * @div: The divisor to calculate the bit information for. - * - * Turn a divisor into the necessary bit field for TCFG1. - */ -static inline unsigned long pwm_tdiv_div_bits(unsigned int div) -{ - return ilog2(div); -} - -#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK - -#endif /* __ASM_ARCH_PWMCLK_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index 78925c516346..032de66fb8be 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -144,8 +144,9 @@ #define S5P_OTHERS S5P_CLKREG(0xE000) #define S5P_OM_STAT S5P_CLKREG(0xE100) +#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) -#define S5P_DAC_CONTROL S5P_CLKREG(0xE810) +#define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE810) #define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814) #define S5P_MIPI_DPHY_ENABLE (1 << 0) #define S5P_MIPI_DPHY_SRESETN (1 << 1) diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index 061cc7e4f48c..15edcae448b9 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c @@ -48,6 +48,11 @@ #include <plat/s5p-time.h> #include <plat/mfc.h> #include <plat/regs-fb-v4.h> +#include <plat/camport.h> + +#include <media/v4l2-mediabus.h> +#include <media/s5p_fimc.h> +#include <media/noon010pc30.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -272,6 +277,14 @@ static void __init goni_tsp_init(void) i2c2_devs[0].irq = gpio_to_irq(gpio); } +static void goni_camera_init(void) +{ + s5pv210_fimc_setup_gpio(S5P_CAMPORT_A); + + /* Set max driver strength on CAM_A_CLKOUT pin. */ + s5p_gpio_set_drvstr(S5PV210_GPE1(3), S5P_GPIO_DRVSTR_LV4); +} + /* MAX8998 regulators */ #if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE) @@ -285,6 +298,7 @@ static struct regulator_consumer_supply goni_ldo5_consumers[] = { static struct regulator_consumer_supply goni_ldo8_consumers[] = { REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), + REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"), }; static struct regulator_consumer_supply goni_ldo11_consumers[] = { @@ -475,6 +489,10 @@ static struct regulator_consumer_supply buck1_consumer = static struct regulator_consumer_supply buck2_consumer = REGULATOR_SUPPLY("vddint", NULL); +static struct regulator_consumer_supply buck3_consumer = + REGULATOR_SUPPLY("vdet", "s5p-sdo"); + + static struct regulator_init_data goni_buck1_data = { .constraints = { .name = "VARM_1.2V", @@ -511,6 +529,8 @@ static struct regulator_init_data goni_buck3_data = { .enabled = 1, }, }, + .num_consumer_supplies = 1, + .consumer_supplies = &buck3_consumer, }; static struct regulator_init_data goni_buck4_data = { @@ -801,6 +821,34 @@ static void goni_setup_sdhci(void) s3c_sdhci2_set_platdata(&goni_hsmmc2_data); }; +static struct noon010pc30_platform_data noon010pc30_pldata = { + .clk_rate = 16000000UL, + .gpio_nreset = S5PV210_GPB(2), /* CAM_CIF_NRST */ + .gpio_nstby = S5PV210_GPB(0), /* CAM_CIF_NSTBY */ +}; + +static struct i2c_board_info noon010pc30_board_info = { + I2C_BOARD_INFO("NOON010PC30", 0x60 >> 1), + .platform_data = &noon010pc30_pldata, +}; + +static struct s5p_fimc_isp_info goni_camera_sensors[] = { + { + .mux_id = 0, + .flags = V4L2_MBUS_PCLK_SAMPLE_FALLING | + V4L2_MBUS_VSYNC_ACTIVE_LOW, + .bus_type = FIMC_ITU_601, + .board_info = &noon010pc30_board_info, + .i2c_bus_num = 0, + .clk_frequency = 16000000UL, + }, +}; + +struct s5p_platform_fimc goni_fimc_md_platdata __initdata = { + .isp_info = goni_camera_sensors, + .num_clients = ARRAY_SIZE(goni_camera_sensors), +}; + static struct platform_device *goni_devices[] __initdata = { &s3c_device_fb, &s5p_device_onenand, @@ -812,10 +860,13 @@ static struct platform_device *goni_devices[] __initdata = { &s5p_device_mfc, &s5p_device_mfc_l, &s5p_device_mfc_r, + &s5p_device_mixer, + &s5p_device_sdo, &s3c_device_i2c0, &s5p_device_fimc0, &s5p_device_fimc1, &s5p_device_fimc2, + &s5p_device_fimc_md, &s3c_device_hsmmc0, &s3c_device_hsmmc1, &s3c_device_hsmmc2, @@ -884,6 +935,12 @@ static void __init goni_machine_init(void) /* FB */ s3c_fb_set_platdata(&goni_lcd_pdata); + /* FIMC */ + s3c_set_platdata(&goni_fimc_md_platdata, sizeof(goni_fimc_md_platdata), + &s5p_device_fimc_md); + + goni_camera_init(); + /* SPI */ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c index a83b6c909f6b..6b8ccc4d35fd 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci.c +++ b/arch/arm/mach-s5pv210/setup-sdhci.c @@ -10,17 +10,7 @@ * published by the Free Software Foundation. */ -#include <linux/kernel.h> #include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/io.h> - -#include <linux/mmc/card.h> -#include <linux/mmc/host.h> - -#include <plat/regs-sdhci.h> -#include <plat/sdhci.h> /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ @@ -30,34 +20,3 @@ char *s5pv210_hsmmc_clksrcs[4] = { [2] = "sclk_mmc", /* mmc_bus */ /* [3] = NULL, - reserved */ }; - -void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card) -{ - u32 ctrl2, ctrl3; - - /* don't need to alter anything according to card-type */ - - writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); - - ctrl2 = readl(r + S3C_SDHCI_CONTROL2); - ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; - ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | - S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | - S3C_SDHCI_CTRL2_ENFBCLKRX | - S3C_SDHCI_CTRL2_DFCNT_NONE | - S3C_SDHCI_CTRL2_ENCLKOUTHOLD); - - if (ios->clock < 25 * 1000000) - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | - S3C_SDHCI_CTRL3_FCSEL2 | - S3C_SDHCI_CTRL3_FCSEL1 | - S3C_SDHCI_CTRL3_FCSEL0); - else - ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); - - writel(ctrl2, r + S3C_SDHCI_CONTROL2); - writel(ctrl3, r + S3C_SDHCI_CONTROL3); -} diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S deleted file mode 100644 index e3452ccd4b08..000000000000 --- a/arch/arm/mach-s5pv210/sleep.S +++ /dev/null @@ -1,52 +0,0 @@ -/* linux/arch/arm/plat-s5p/sleep.S - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * S5PV210 power Manager (Suspend-To-RAM) support - * Based on S3C2410 sleep code by: - * Ben Dooks, (c) 2004 Simtec Electronics - * - * Based on PXA/SA1100 sleep code by: - * Nicolas Pitre, (c) 2002 Monta Vista Software Inc - * Cliff Brake, (c) 2001 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/linkage.h> -#include <asm/assembler.h> -#include <asm/memory.h> - - .text - - /* sleep magic, to allow the bootloader to check for an valid - * image to resume to. Must be the first word before the - * s3c_cpu_resume entry. - */ - - .word 0x2bedf00d - - /* s3c_cpu_resume - * - * resume code entry for bootloader to call - * - * we must put this code here in the data segment as we have no - * other way of restoring the stack pointer after sleep, and we - * must not write to the code segment (code is read-only) - */ - -ENTRY(s3c_cpu_resume) - b cpu_resume diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 8c5b3029b39f..d8973ac46bc4 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -9,7 +9,6 @@ config PLAT_S3C24XX select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select S3C_DEV_NAND - select S3C_GPIO_CFG_S3C24XX help Base platform code for any Samsung S3C24XX device diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 0291bd6e236e..b2b01125de66 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -14,9 +14,7 @@ obj- := obj-y += cpu.o obj-y += irq.o -obj-y += devs.o -obj-y += gpio.o -obj-y += gpiolib.o +obj-y += dev-uart.o obj-y += clock.o obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o diff --git a/arch/arm/plat-s3c24xx/dev-uart.c b/arch/arm/plat-s3c24xx/dev-uart.c new file mode 100644 index 000000000000..9ab22e662fff --- /dev/null +++ b/arch/arm/plat-s3c24xx/dev-uart.c @@ -0,0 +1,100 @@ +/* linux/arch/arm/plat-s3c24xx/dev-uart.c + * + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * Base S3C24XX UART resource and platform device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> +#include <mach/hardware.h> +#include <mach/map.h> + +#include <plat/devs.h> +#include <plat/regs-serial.h> + +/* Serial port registrations */ + +static struct resource s3c2410_uart0_resource[] = { + [0] = { + .start = S3C2410_PA_UART0, + .end = S3C2410_PA_UART0 + 0x3fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX0, + .end = IRQ_S3CUART_ERR0, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource s3c2410_uart1_resource[] = { + [0] = { + .start = S3C2410_PA_UART1, + .end = S3C2410_PA_UART1 + 0x3fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX1, + .end = IRQ_S3CUART_ERR1, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource s3c2410_uart2_resource[] = { + [0] = { + .start = S3C2410_PA_UART2, + .end = S3C2410_PA_UART2 + 0x3fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX2, + .end = IRQ_S3CUART_ERR2, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource s3c2410_uart3_resource[] = { + [0] = { + .start = S3C2443_PA_UART3, + .end = S3C2443_PA_UART3 + 0x3fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S3CUART_RX3, + .end = IRQ_S3CUART_ERR3, + .flags = IORESOURCE_IRQ, + }, +}; + +struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { + [0] = { + .resources = s3c2410_uart0_resource, + .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource), + }, + [1] = { + .resources = s3c2410_uart1_resource, + .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource), + }, + [2] = { + .resources = s3c2410_uart2_resource, + .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), + }, + [3] = { + .resources = s3c2410_uart3_resource, + .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource), + }, +}; diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c deleted file mode 100644 index a76bf2df3333..000000000000 --- a/arch/arm/plat-s3c24xx/devs.c +++ /dev/null @@ -1,528 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/devs.c - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * Base S3C24XX platform device definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * -*/ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/list.h> -#include <linux/timer.h> -#include <linux/init.h> -#include <linux/serial_core.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/string.h> -#include <linux/dma-mapping.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> -#include <mach/fb.h> -#include <mach/hardware.h> -#include <mach/dma.h> -#include <mach/irqs.h> -#include <asm/irq.h> - -#include <plat/regs-serial.h> -#include <plat/udc.h> -#include <plat/mci.h> - -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/regs-spi.h> -#include <plat/ts.h> - -/* Serial port registrations */ - -static struct resource s3c2410_uart0_resource[] = { - [0] = { - .start = S3C2410_PA_UART0, - .end = S3C2410_PA_UART0 + 0x3fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX0, - .end = IRQ_S3CUART_ERR0, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource s3c2410_uart1_resource[] = { - [0] = { - .start = S3C2410_PA_UART1, - .end = S3C2410_PA_UART1 + 0x3fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX1, - .end = IRQ_S3CUART_ERR1, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource s3c2410_uart2_resource[] = { - [0] = { - .start = S3C2410_PA_UART2, - .end = S3C2410_PA_UART2 + 0x3fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX2, - .end = IRQ_S3CUART_ERR2, - .flags = IORESOURCE_IRQ, - } -}; - -static struct resource s3c2410_uart3_resource[] = { - [0] = { - .start = S3C2443_PA_UART3, - .end = S3C2443_PA_UART3 + 0x3fff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3CUART_RX3, - .end = IRQ_S3CUART_ERR3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { - [0] = { - .resources = s3c2410_uart0_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource), - }, - [1] = { - .resources = s3c2410_uart1_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource), - }, - [2] = { - .resources = s3c2410_uart2_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), - }, - [3] = { - .resources = s3c2410_uart3_resource, - .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource), - }, -}; - -/* LCD Controller */ - -static struct resource s3c_lcd_resource[] = { - [0] = { - .start = S3C24XX_PA_LCD, - .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_LCD, - .end = IRQ_LCD, - .flags = IORESOURCE_IRQ, - } - -}; - -static u64 s3c_device_lcd_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_lcd = { - .name = "s3c2410-lcd", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_lcd_resource), - .resource = s3c_lcd_resource, - .dev = { - .dma_mask = &s3c_device_lcd_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_lcd); - -void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) -{ - struct s3c2410fb_mach_info *npd; - - npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd); - if (npd) { - npd->displays = kmemdup(pd->displays, - sizeof(struct s3c2410fb_display) * npd->num_displays, - GFP_KERNEL); - if (!npd->displays) - printk(KERN_ERR "no memory for LCD display data\n"); - } else { - printk(KERN_ERR "no memory for LCD platform data\n"); - } -} - -/* Touchscreen */ - -static struct resource s3c_ts_resource[] = { - [0] = { - .start = S3C24XX_PA_ADC, - .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TC, - .end = IRQ_TC, - .flags = IORESOURCE_IRQ, - }, - -}; - -struct platform_device s3c_device_ts = { - .name = "s3c2410-ts", - .id = -1, - .dev.parent = &s3c_device_adc.dev, - .num_resources = ARRAY_SIZE(s3c_ts_resource), - .resource = s3c_ts_resource, -}; -EXPORT_SYMBOL(s3c_device_ts); - -void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info) -{ - s3c_set_platdata(hard_s3c2410ts_info, - sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts); -} - -/* USB Device (Gadget)*/ - -static struct resource s3c_usbgadget_resource[] = { - [0] = { - .start = S3C24XX_PA_USBDEV, - .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USBD, - .end = IRQ_USBD, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_usbgadget = { - .name = "s3c2410-usbgadget", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_usbgadget_resource), - .resource = s3c_usbgadget_resource, -}; - -EXPORT_SYMBOL(s3c_device_usbgadget); - -void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd) -{ - s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget); -} - -/* USB High Speed 2.0 Device (Gadget) */ -static struct resource s3c_hsudc_resource[] = { - [0] = { - .start = S3C2416_PA_HSUDC, - .end = S3C2416_PA_HSUDC + S3C2416_SZ_HSUDC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USBD, - .end = IRQ_USBD, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_hsudc_dmamask = DMA_BIT_MASK(32); - -struct platform_device s3c_device_usb_hsudc = { - .name = "s3c-hsudc", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_hsudc_resource), - .resource = s3c_hsudc_resource, - .dev = { - .dma_mask = &s3c_hsudc_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd) -{ - s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc); -} - -/* IIS */ - -static struct resource s3c_iis_resource[] = { - [0] = { - .start = S3C24XX_PA_IIS, - .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1, - .flags = IORESOURCE_MEM, - } -}; - -static u64 s3c_device_iis_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_iis = { - .name = "s3c24xx-iis", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_iis_resource), - .resource = s3c_iis_resource, - .dev = { - .dma_mask = &s3c_device_iis_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_iis); - -/* RTC */ - -static struct resource s3c_rtc_resource[] = { - [0] = { - .start = S3C24XX_PA_RTC, - .end = S3C24XX_PA_RTC + 0xff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_RTC, - .end = IRQ_RTC, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_TICK, - .end = IRQ_TICK, - .flags = IORESOURCE_IRQ - } -}; - -struct platform_device s3c_device_rtc = { - .name = "s3c2410-rtc", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_rtc_resource), - .resource = s3c_rtc_resource, -}; - -EXPORT_SYMBOL(s3c_device_rtc); - -/* ADC */ - -static struct resource s3c_adc_resource[] = { - [0] = { - .start = S3C24XX_PA_ADC, - .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TC, - .end = IRQ_TC, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_ADC, - .end = IRQ_ADC, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_adc = { - .name = "s3c24xx-adc", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_adc_resource), - .resource = s3c_adc_resource, -}; - -/* SDI */ - -static struct resource s3c_sdi_resource[] = { - [0] = { - .start = S3C24XX_PA_SDI, - .end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SDI, - .end = IRQ_SDI, - .flags = IORESOURCE_IRQ, - } - -}; - -struct platform_device s3c_device_sdi = { - .name = "s3c2410-sdi", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_sdi_resource), - .resource = s3c_sdi_resource, -}; - -EXPORT_SYMBOL(s3c_device_sdi); - -void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) -{ - s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata), - &s3c_device_sdi); -} - - -/* SPI (0) */ - -static struct resource s3c_spi0_resource[] = { - [0] = { - .start = S3C24XX_PA_SPI, - .end = S3C24XX_PA_SPI + 0x1f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SPI0, - .end = IRQ_SPI0, - .flags = IORESOURCE_IRQ, - } - -}; - -static u64 s3c_device_spi0_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_spi0 = { - .name = "s3c2410-spi", - .id = 0, - .num_resources = ARRAY_SIZE(s3c_spi0_resource), - .resource = s3c_spi0_resource, - .dev = { - .dma_mask = &s3c_device_spi0_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_spi0); - -/* SPI (1) */ - -static struct resource s3c_spi1_resource[] = { - [0] = { - .start = S3C24XX_PA_SPI + S3C2410_SPI1, - .end = S3C24XX_PA_SPI + S3C2410_SPI1 + 0x1f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_SPI1, - .end = IRQ_SPI1, - .flags = IORESOURCE_IRQ, - } - -}; - -static u64 s3c_device_spi1_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_spi1 = { - .name = "s3c2410-spi", - .id = 1, - .num_resources = ARRAY_SIZE(s3c_spi1_resource), - .resource = s3c_spi1_resource, - .dev = { - .dma_mask = &s3c_device_spi1_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_spi1); - -#ifdef CONFIG_CPU_S3C2440 - -/* Camif Controller */ - -static struct resource s3c_camif_resource[] = { - [0] = { - .start = S3C2440_PA_CAMIF, - .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CAM, - .end = IRQ_CAM, - .flags = IORESOURCE_IRQ, - } - -}; - -static u64 s3c_device_camif_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_camif = { - .name = "s3c2440-camif", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_camif_resource), - .resource = s3c_camif_resource, - .dev = { - .dma_mask = &s3c_device_camif_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_camif); - -/* AC97 */ - -static struct resource s3c_ac97_resource[] = { - [0] = { - .start = S3C2440_PA_AC97, - .end = S3C2440_PA_AC97 + S3C2440_SZ_AC97 -1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_S3C244x_AC97, - .end = IRQ_S3C244x_AC97, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .name = "PCM out", - .start = DMACH_PCM_OUT, - .end = DMACH_PCM_OUT, - .flags = IORESOURCE_DMA, - }, - [3] = { - .name = "PCM in", - .start = DMACH_PCM_IN, - .end = DMACH_PCM_IN, - .flags = IORESOURCE_DMA, - }, - [4] = { - .name = "Mic in", - .start = DMACH_MIC_IN, - .end = DMACH_MIC_IN, - .flags = IORESOURCE_DMA, - }, -}; - -static u64 s3c_device_audio_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_ac97 = { - .name = "samsung-ac97", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_ac97_resource), - .resource = s3c_ac97_resource, - .dev = { - .dma_mask = &s3c_device_audio_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_ac97); - -/* ASoC I2S */ - -struct platform_device s3c2412_device_iis = { - .name = "s3c2412-iis", - .id = -1, - .dev = { - .dma_mask = &s3c_device_audio_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c2412_device_iis); - -#endif // CONFIG_CPU_S32440 diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c deleted file mode 100644 index 2f3d7c089dfa..000000000000 --- a/arch/arm/plat-s3c24xx/gpio.c +++ /dev/null @@ -1,96 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/gpio.c - * - * Copyright (c) 2004-2010 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C24XX GPIO support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <linux/gpio.h> -#include <linux/io.h> - -#include <mach/hardware.h> -#include <mach/gpio-fns.h> -#include <asm/irq.h> - -#include <mach/regs-gpio.h> - -#include <plat/gpio-core.h> - -/* gpiolib wrappers until these are totally eliminated */ - -void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) -{ - int ret; - - WARN_ON(to); /* should be none of these left */ - - if (!to) { - /* if pull is enabled, try first with up, and if that - * fails, try using down */ - - ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP); - if (ret) - s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN); - } else { - s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE); - } -} -EXPORT_SYMBOL(s3c2410_gpio_pullup); - -void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) -{ - /* do this via gpiolib until all users removed */ - - gpio_request(pin, "temporary"); - gpio_set_value(pin, to); - gpio_free(pin); -} - -EXPORT_SYMBOL(s3c2410_gpio_setpin); - -unsigned int s3c2410_gpio_getpin(unsigned int pin) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - unsigned long offs = pin - chip->chip.base; - - return __raw_readl(chip->base + 0x04) & (1<< offs); -} - -EXPORT_SYMBOL(s3c2410_gpio_getpin); - -unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) -{ - unsigned long flags; - unsigned long misccr; - - local_irq_save(flags); - misccr = __raw_readl(S3C24XX_MISCCR); - misccr &= ~clear; - misccr ^= change; - __raw_writel(misccr, S3C24XX_MISCCR); - local_irq_restore(flags); - - return misccr; -} - -EXPORT_SYMBOL(s3c2410_modify_misccr); diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c deleted file mode 100644 index 243b6411050d..000000000000 --- a/arch/arm/plat-s3c24xx/gpiolib.c +++ /dev/null @@ -1,229 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/gpiolib.c - * - * Copyright (c) 2008-2010 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C24XX GPIOlib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/interrupt.h> -#include <linux/sysdev.h> -#include <linux/ioport.h> -#include <linux/io.h> -#include <linux/gpio.h> - -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> -#include <mach/hardware.h> -#include <asm/irq.h> -#include <plat/pm.h> - -#include <mach/regs-gpio.h> - -static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) -{ - return -EINVAL; -} - -static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long flags; - unsigned long dat; - unsigned long con; - - local_irq_save(flags); - - con = __raw_readl(base + 0x00); - dat = __raw_readl(base + 0x04); - - dat &= ~(1 << offset); - if (value) - dat |= 1 << offset; - - __raw_writel(dat, base + 0x04); - - con &= ~(1 << offset); - - __raw_writel(con, base + 0x00); - __raw_writel(dat, base + 0x04); - - local_irq_restore(flags); - return 0; -} - -static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset) -{ - if (offset < 4) - return IRQ_EINT0 + offset; - - if (offset < 8) - return IRQ_EINT4 + offset - 4; - - return -EINVAL; -} - -static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = { - .set_config = s3c_gpio_setcfg_s3c24xx_a, - .get_config = s3c_gpio_getcfg_s3c24xx_a, -}; - -struct s3c_gpio_cfg s3c24xx_gpiocfg_default = { - .set_config = s3c_gpio_setcfg_s3c24xx, - .get_config = s3c_gpio_getcfg_s3c24xx, -}; - -struct s3c_gpio_chip s3c24xx_gpios[] = { - [0] = { - .base = S3C2410_GPACON, - .pm = __gpio_pm(&s3c_gpio_pm_1bit), - .config = &s3c24xx_gpiocfg_banka, - .chip = { - .base = S3C2410_GPA(0), - .owner = THIS_MODULE, - .label = "GPIOA", - .ngpio = 24, - .direction_input = s3c24xx_gpiolib_banka_input, - .direction_output = s3c24xx_gpiolib_banka_output, - }, - }, - [1] = { - .base = S3C2410_GPBCON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .chip = { - .base = S3C2410_GPB(0), - .owner = THIS_MODULE, - .label = "GPIOB", - .ngpio = 16, - }, - }, - [2] = { - .base = S3C2410_GPCCON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .chip = { - .base = S3C2410_GPC(0), - .owner = THIS_MODULE, - .label = "GPIOC", - .ngpio = 16, - }, - }, - [3] = { - .base = S3C2410_GPDCON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .chip = { - .base = S3C2410_GPD(0), - .owner = THIS_MODULE, - .label = "GPIOD", - .ngpio = 16, - }, - }, - [4] = { - .base = S3C2410_GPECON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .chip = { - .base = S3C2410_GPE(0), - .label = "GPIOE", - .owner = THIS_MODULE, - .ngpio = 16, - }, - }, - [5] = { - .base = S3C2410_GPFCON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .chip = { - .base = S3C2410_GPF(0), - .owner = THIS_MODULE, - .label = "GPIOF", - .ngpio = 8, - .to_irq = s3c24xx_gpiolib_bankf_toirq, - }, - }, - [6] = { - .base = S3C2410_GPGCON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .irq_base = IRQ_EINT8, - .chip = { - .base = S3C2410_GPG(0), - .owner = THIS_MODULE, - .label = "GPIOG", - .ngpio = 16, - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = S3C2410_GPHCON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .chip = { - .base = S3C2410_GPH(0), - .owner = THIS_MODULE, - .label = "GPIOH", - .ngpio = 11, - }, - }, - /* GPIOS for the S3C2443 and later devices. */ - { - .base = S3C2440_GPJCON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .chip = { - .base = S3C2410_GPJ(0), - .owner = THIS_MODULE, - .label = "GPIOJ", - .ngpio = 16, - }, - }, { - .base = S3C2443_GPKCON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .chip = { - .base = S3C2410_GPK(0), - .owner = THIS_MODULE, - .label = "GPIOK", - .ngpio = 16, - }, - }, { - .base = S3C2443_GPLCON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .chip = { - .base = S3C2410_GPL(0), - .owner = THIS_MODULE, - .label = "GPIOL", - .ngpio = 15, - }, - }, { - .base = S3C2443_GPMCON, - .pm = __gpio_pm(&s3c_gpio_pm_2bit), - .chip = { - .base = S3C2410_GPM(0), - .owner = THIS_MODULE, - .label = "GPIOM", - .ngpio = 2, - }, - }, -}; - - -static __init int s3c24xx_gpiolib_init(void) -{ - struct s3c_gpio_chip *chip = s3c24xx_gpios; - int gpn; - - for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) { - if (!chip->config) - chip->config = &s3c24xx_gpiocfg_default; - - s3c_gpiolib_add(chip); - } - - return 0; -} - -core_initcall(s3c24xx_gpiolib_init); diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h b/arch/arm/plat-s3c24xx/include/mach/clkdev.h deleted file mode 100644 index 7dffa83d23ff..000000000000 --- a/arch/arm/plat-s3c24xx/include/mach/clkdev.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __MACH_CLKDEV_H__ -#define __MACH_CLKDEV_H__ - -#define __clk_get(clk) ({ 1; }) -#define __clk_put(clk) do {} while (0) - -#endif diff --git a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h deleted file mode 100644 index a087de21bc20..000000000000 --- a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h +++ /dev/null @@ -1,55 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C24xx - pwm clock and timer support - */ - -/** - * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk - * @cfg: The timer TCFG1 register bits shifted down to 0. - * - * Return true if the given configuration from TCFG1 is a TCLK instead - * any of the TDIV clocks. - */ -static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) -{ - return tcfg == S3C2410_TCFG1_MUX_TCLK; -} - -/** - * tcfg_to_divisor() - convert tcfg1 setting to a divisor - * @tcfg1: The tcfg1 setting, shifted down. - * - * Get the divisor value for the given tcfg1 setting. We assume the - * caller has already checked to see if this is not a TCLK source. - */ -static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) -{ - return 1 << (1 + tcfg1); -} - -/** - * pwm_tdiv_has_div1() - does the tdiv setting have a /1 - * - * Return true if we have a /1 in the tdiv setting. - */ -static inline unsigned int pwm_tdiv_has_div1(void) -{ - return 0; -} - -/** - * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. - * @div: The divisor to calculate the bit information for. - * - * Turn a divisor into the necessary bit field for TCFG1. - */ -static inline unsigned long pwm_tdiv_div_bits(unsigned int div) -{ - return ilog2(div) - 1; -} - -#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h deleted file mode 100644 index 005729a1077a..000000000000 --- a/arch/arm/plat-s3c24xx/include/plat/pll.h +++ /dev/null @@ -1,62 +0,0 @@ -/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C24xx - common pll registers and code - */ - -#define S3C24XX_PLLCON_MDIVSHIFT 12 -#define S3C24XX_PLLCON_PDIVSHIFT 4 -#define S3C24XX_PLLCON_SDIVSHIFT 0 -#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) -#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1) -#define S3C24XX_PLLCON_SDIVMASK 3 - -#include <asm/div64.h> - -static inline unsigned int -s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int mdiv, pdiv, sdiv; - uint64_t fvco; - - mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT; - pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT; - sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT; - - mdiv &= S3C24XX_PLLCON_MDIVMASK; - pdiv &= S3C24XX_PLLCON_PDIVMASK; - sdiv &= S3C24XX_PLLCON_SDIVMASK; - - fvco = (uint64_t)baseclk * (mdiv + 8); - do_div(fvco, (pdiv + 2) << sdiv); - - return (unsigned int)fvco; -} - -#define S3C2416_PLL_M_SHIFT (14) -#define S3C2416_PLL_P_SHIFT (5) -#define S3C2416_PLL_S_MASK (7) -#define S3C2416_PLL_M_MASK ((1 << 10) - 1) -#define S3C2416_PLL_P_MASK (63) - -static inline unsigned int -s3c2416_get_pll(unsigned int pllval, unsigned int baseclk) -{ - unsigned int m, p, s; - uint64_t fvco; - - m = pllval >> S3C2416_PLL_M_SHIFT; - p = pllval >> S3C2416_PLL_P_SHIFT; - - s = pllval & S3C2416_PLL_S_MASK; - m &= S3C2416_PLL_M_MASK; - p &= S3C2416_PLL_P_MASK; - - fvco = (uint64_t)baseclk * m; - do_div(fvco, (p << s)); - - return (unsigned int)fvco; -} diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h deleted file mode 100644 index cc44e0e931e9..000000000000 --- a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h +++ /dev/null @@ -1,68 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-iis.h - * - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 IIS register definition -*/ - -#ifndef __ASM_ARCH_REGS_IIS_H -#define __ASM_ARCH_REGS_IIS_H - -#define S3C2410_IISCON (0x00) - -#define S3C2410_IISCON_LRINDEX (1<<8) -#define S3C2410_IISCON_TXFIFORDY (1<<7) -#define S3C2410_IISCON_RXFIFORDY (1<<6) -#define S3C2410_IISCON_TXDMAEN (1<<5) -#define S3C2410_IISCON_RXDMAEN (1<<4) -#define S3C2410_IISCON_TXIDLE (1<<3) -#define S3C2410_IISCON_RXIDLE (1<<2) -#define S3C2410_IISCON_PSCEN (1<<1) -#define S3C2410_IISCON_IISEN (1<<0) - -#define S3C2410_IISMOD (0x04) - -#define S3C2440_IISMOD_MPLL (1<<9) -#define S3C2410_IISMOD_SLAVE (1<<8) -#define S3C2410_IISMOD_NOXFER (0<<6) -#define S3C2410_IISMOD_RXMODE (1<<6) -#define S3C2410_IISMOD_TXMODE (2<<6) -#define S3C2410_IISMOD_TXRXMODE (3<<6) -#define S3C2410_IISMOD_LR_LLOW (0<<5) -#define S3C2410_IISMOD_LR_RLOW (1<<5) -#define S3C2410_IISMOD_IIS (0<<4) -#define S3C2410_IISMOD_MSB (1<<4) -#define S3C2410_IISMOD_8BIT (0<<3) -#define S3C2410_IISMOD_16BIT (1<<3) -#define S3C2410_IISMOD_BITMASK (1<<3) -#define S3C2410_IISMOD_256FS (0<<2) -#define S3C2410_IISMOD_384FS (1<<2) -#define S3C2410_IISMOD_16FS (0<<0) -#define S3C2410_IISMOD_32FS (1<<0) -#define S3C2410_IISMOD_48FS (2<<0) -#define S3C2410_IISMOD_FS_MASK (3<<0) - -#define S3C2410_IISPSR (0x08) -#define S3C2410_IISPSR_INTMASK (31<<5) -#define S3C2410_IISPSR_INTSHIFT (5) -#define S3C2410_IISPSR_EXTMASK (31<<0) -#define S3C2410_IISPSR_EXTSHFIT (0) - -#define S3C2410_IISFCON (0x0c) - -#define S3C2410_IISFCON_TXDMA (1<<15) -#define S3C2410_IISFCON_RXDMA (1<<14) -#define S3C2410_IISFCON_TXENABLE (1<<13) -#define S3C2410_IISFCON_RXENABLE (1<<12) -#define S3C2410_IISFCON_TXMASK (0x3f << 6) -#define S3C2410_IISFCON_TXSHIFT (6) -#define S3C2410_IISFCON_RXMASK (0x3f) -#define S3C2410_IISFCON_RXSHIFT (0) - -#define S3C2410_IISFIFO (0x10) -#endif /* __ASM_ARCH_REGS_IIS_H */ diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h deleted file mode 100644 index 892e2f680fca..000000000000 --- a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h +++ /dev/null @@ -1,81 +0,0 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-spi.h - * - * Copyright (c) 2004 Fetron GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * S3C2410 SPI register definition -*/ - -#ifndef __ASM_ARCH_REGS_SPI_H -#define __ASM_ARCH_REGS_SPI_H - -#define S3C2410_SPI1 (0x20) -#define S3C2412_SPI1 (0x100) - -#define S3C2410_SPCON (0x00) - -#define S3C2412_SPCON_RXFIFO_RB2 (0<<14) -#define S3C2412_SPCON_RXFIFO_RB4 (1<<14) -#define S3C2412_SPCON_RXFIFO_RB12 (2<<14) -#define S3C2412_SPCON_RXFIFO_RB14 (3<<14) -#define S3C2412_SPCON_TXFIFO_RB2 (0<<12) -#define S3C2412_SPCON_TXFIFO_RB4 (1<<12) -#define S3C2412_SPCON_TXFIFO_RB12 (2<<12) -#define S3C2412_SPCON_TXFIFO_RB14 (3<<12) -#define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */ -#define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */ -#define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */ -#define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */ - -#define S3C2412_SPCON_DIRC_RX (1<<7) - -#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */ -#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */ -#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */ -#define S3C2410_SPCON_ENSCK (1<<4) /* Enable SCK */ -#define S3C2410_SPCON_MSTR (1<<3) /* Master/Slave select - 0: slave, 1: master */ -#define S3C2410_SPCON_CPOL_HIGH (1<<2) /* Clock polarity select */ -#define S3C2410_SPCON_CPOL_LOW (0<<2) /* Clock polarity select */ - -#define S3C2410_SPCON_CPHA_FMTB (1<<1) /* Clock Phase Select */ -#define S3C2410_SPCON_CPHA_FMTA (0<<1) /* Clock Phase Select */ - -#define S3C2410_SPCON_TAGD (1<<0) /* Tx auto garbage data mode */ - - -#define S3C2410_SPSTA (0x04) - -#define S3C2412_SPSTA_RXFIFO_AE (1<<11) -#define S3C2412_SPSTA_TXFIFO_AE (1<<10) -#define S3C2412_SPSTA_RXFIFO_ERROR (1<<9) -#define S3C2412_SPSTA_TXFIFO_ERROR (1<<8) -#define S3C2412_SPSTA_RXFIFO_FIFO (1<<7) -#define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6) -#define S3C2412_SPSTA_TXFIFO_NFULL (1<<5) -#define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4) - -#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */ -#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */ -#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */ -#define S3C2412_SPSTA_READY_ORG (1<<3) - -#define S3C2410_SPPIN (0x08) - -#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */ -#define S3C2410_SPPIN_RESERVED (1<<1) -#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */ - -#define S3C2410_SPPRE (0x0C) -#define S3C2410_SPTDAT (0x10) -#define S3C2410_SPRDAT (0x14) - -#define S3C2412_TXFIFO (0x18) -#define S3C2412_RXFIFO (0x18) -#define S3C2412_SPFIC (0x24) - - -#endif /* __ASM_ARCH_REGS_SPI_H */ diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c index 59552c0ea5fb..07a4c81587ac 100644 --- a/arch/arm/plat-s3c24xx/s3c2443-clock.c +++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c @@ -205,9 +205,64 @@ static struct clksrc_clk clksrc_clks[] = { }, }; +static struct clk clk_i2s_ext = { + .name = "i2s-ext", +}; + +/* i2s_eplldiv + * + * This clock is the output from the I2S divisor of ESYSCLK, and is separate + * from the mux that comes after it (cannot merge into one single clock) +*/ + +static struct clksrc_clk clk_i2s_eplldiv = { + .clk = { + .name = "i2s-eplldiv", + .parent = &clk_esysclk.clk, + }, + .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, }, +}; + +/* i2s-ref + * + * i2s bus reference clock, selectable from external, esysclk or epllref + * + * Note, this used to be two clocks, but was compressed into one. +*/ + +static struct clk *clk_i2s_srclist[] = { + [0] = &clk_i2s_eplldiv.clk, + [1] = &clk_i2s_ext, + [2] = &clk_epllref.clk, + [3] = &clk_epllref.clk, +}; + +static struct clksrc_clk clk_i2s = { + .clk = { + .name = "i2s-if", + .ctrlbit = S3C2443_SCLKCON_I2SCLK, + .enable = s3c2443_clkcon_enable_s, + + }, + .sources = &(struct clksrc_sources) { + .sources = clk_i2s_srclist, + .nr_sources = ARRAY_SIZE(clk_i2s_srclist), + }, + .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 }, +}; static struct clk init_clocks_off[] = { { + .name = "iis", + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_IIS, + }, { + .name = "hsspi", + .parent = &clk_p, + .enable = s3c2443_clkcon_enable_p, + .ctrlbit = S3C2443_PCLKCON_HSSPI, + }, { .name = "adc", .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, @@ -406,6 +461,8 @@ static struct clk *clks[] __initdata = { }; static struct clksrc_clk *clksrcs[] __initdata = { + &clk_i2s_eplldiv, + &clk_i2s, &clk_usb_bus_host, &clk_epllref, &clk_esysclk, diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 9a197e55f669..ab16e5568c4c 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -16,9 +16,6 @@ config PLAT_S5P select S3C_GPIO_TRACK select S5P_GPIO_DRVSTR select SAMSUNG_GPIOLIB_4BIT - select S3C_GPIO_CFG_S3C64XX - select S3C_GPIO_PULL_UPDOWN - select S3C_GPIO_CFG_S3C24XX select PLAT_SAMSUNG select SAMSUNG_CLKSRC select SAMSUNG_IRQ_VIC_TIMER @@ -42,6 +39,12 @@ config S5P_HRT help Use the High Resolution timer support +config S5P_PM + bool + help + Common code for power management support on S5P and newer SoCs + Note: Do not select this for S5P6440 and S5P6450. + comment "System MMU" config S5P_SYSTEM_MMU @@ -50,6 +53,12 @@ config S5P_SYSTEM_MMU help Say Y here if you want to enable System MMU +config S5P_SLEEP + bool + help + Internal config node to apply common S5P sleep management code. + Can be selected by S5P and newer SoCs with similar sleep procedure. + config S5P_DEV_FIMC0 bool help @@ -75,6 +84,11 @@ config S5P_DEV_FIMD0 help Compile in platform device definitions for FIMD controller 0 +config S5P_DEV_I2C_HDMIPHY + bool + help + Compile in platform device definitions for I2C HDMIPHY controller + config S5P_DEV_MFC bool help @@ -95,6 +109,11 @@ config S5P_DEV_CSIS1 help Compile in platform device definitions for MIPI-CSIS channel 1 +config S5P_DEV_TV + bool + help + Compile in platform device definition for TV interface + config S5P_DEV_USB_EHCI bool help diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index 4b53e04eeca4..876344038b8d 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -12,7 +12,6 @@ obj- := # Core files -obj-y += dev-pmu.o obj-y += dev-uart.o obj-y += cpu.o obj-y += clock.o @@ -20,19 +19,10 @@ obj-y += irq.o obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o obj-$(CONFIG_S5P_SYSTEM_MMU) += sysmmu.o -obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += irq-pm.o +obj-$(CONFIG_S5P_PM) += pm.o irq-pm.o +obj-$(CONFIG_S5P_SLEEP) += sleep.o obj-$(CONFIG_S5P_HRT) += s5p-time.o # devices obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o -obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o -obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o -obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o -obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o -obj-$(CONFIG_S5P_DEV_FIMD0) += dev-fimd0.o -obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o -obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o -obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o -obj-$(CONFIG_S5P_DEV_USB_EHCI) += dev-ehci.o obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c deleted file mode 100644 index e3aabef5e347..000000000000 --- a/arch/arm/plat-s5p/dev-csis0.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd. - * - * S5P series device definition for MIPI-CSIS channel 0 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <mach/map.h> - -static struct resource s5p_mipi_csis0_resource[] = { - [0] = { - .start = S5P_PA_MIPI_CSIS0, - .end = S5P_PA_MIPI_CSIS0 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_MIPI_CSIS0, - .end = IRQ_MIPI_CSIS0, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device s5p_device_mipi_csis0 = { - .name = "s5p-mipi-csis", - .id = 0, - .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource), - .resource = s5p_mipi_csis0_resource, -}; diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c deleted file mode 100644 index 08b91b580207..000000000000 --- a/arch/arm/plat-s5p/dev-csis1.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd. - * - * S5P series device definition for MIPI-CSIS channel 1 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <mach/map.h> - -static struct resource s5p_mipi_csis1_resource[] = { - [0] = { - .start = S5P_PA_MIPI_CSIS1, - .end = S5P_PA_MIPI_CSIS1 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_MIPI_CSIS1, - .end = IRQ_MIPI_CSIS1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s5p_device_mipi_csis1 = { - .name = "s5p-mipi-csis", - .id = 1, - .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource), - .resource = s5p_mipi_csis1_resource, -}; diff --git a/arch/arm/plat-s5p/dev-ehci.c b/arch/arm/plat-s5p/dev-ehci.c deleted file mode 100644 index 94080fff9e9b..000000000000 --- a/arch/arm/plat-s5p/dev-ehci.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (C) 2011 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim <jy0922.shim@samsung.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include <linux/platform_device.h> -#include <mach/irqs.h> -#include <mach/map.h> -#include <plat/devs.h> -#include <plat/ehci.h> -#include <plat/usb-phy.h> - -/* USB EHCI Host Controller registration */ -static struct resource s5p_ehci_resource[] = { - [0] = { - .start = S5P_PA_EHCI, - .end = S5P_PA_EHCI + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USB_HOST, - .end = IRQ_USB_HOST, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s5p_device_ehci_dmamask = 0xffffffffUL; - -struct platform_device s5p_device_ehci = { - .name = "s5p-ehci", - .id = -1, - .num_resources = ARRAY_SIZE(s5p_ehci_resource), - .resource = s5p_ehci_resource, - .dev = { - .dma_mask = &s5p_device_ehci_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd) -{ - struct s5p_ehci_platdata *npd; - - npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata), - &s5p_device_ehci); - - if (!npd->phy_init) - npd->phy_init = s5p_usb_phy_init; - if (!npd->phy_exit) - npd->phy_exit = s5p_usb_phy_exit; -} diff --git a/arch/arm/plat-s5p/dev-fimc0.c b/arch/arm/plat-s5p/dev-fimc0.c deleted file mode 100644 index 608770fc1531..000000000000 --- a/arch/arm/plat-s5p/dev-fimc0.c +++ /dev/null @@ -1,43 +0,0 @@ -/* linux/arch/arm/plat-s5p/dev-fimc0.c - * - * Copyright (c) 2010 Samsung Electronics - * - * Base S5P FIMC0 resource and device definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <mach/map.h> - -static struct resource s5p_fimc0_resource[] = { - [0] = { - .start = S5P_PA_FIMC0, - .end = S5P_PA_FIMC0 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_FIMC0, - .end = IRQ_FIMC0, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 s5p_fimc0_dma_mask = DMA_BIT_MASK(32); - -struct platform_device s5p_device_fimc0 = { - .name = "s5p-fimc", - .id = 0, - .num_resources = ARRAY_SIZE(s5p_fimc0_resource), - .resource = s5p_fimc0_resource, - .dev = { - .dma_mask = &s5p_fimc0_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/plat-s5p/dev-fimc1.c b/arch/arm/plat-s5p/dev-fimc1.c deleted file mode 100644 index 76e3a97a87d3..000000000000 --- a/arch/arm/plat-s5p/dev-fimc1.c +++ /dev/null @@ -1,43 +0,0 @@ -/* linux/arch/arm/plat-s5p/dev-fimc1.c - * - * Copyright (c) 2010 Samsung Electronics - * - * Base S5P FIMC1 resource and device definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <mach/map.h> - -static struct resource s5p_fimc1_resource[] = { - [0] = { - .start = S5P_PA_FIMC1, - .end = S5P_PA_FIMC1 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_FIMC1, - .end = IRQ_FIMC1, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 s5p_fimc1_dma_mask = DMA_BIT_MASK(32); - -struct platform_device s5p_device_fimc1 = { - .name = "s5p-fimc", - .id = 1, - .num_resources = ARRAY_SIZE(s5p_fimc1_resource), - .resource = s5p_fimc1_resource, - .dev = { - .dma_mask = &s5p_fimc1_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/plat-s5p/dev-fimc2.c b/arch/arm/plat-s5p/dev-fimc2.c deleted file mode 100644 index 24d29816fa2c..000000000000 --- a/arch/arm/plat-s5p/dev-fimc2.c +++ /dev/null @@ -1,43 +0,0 @@ -/* linux/arch/arm/plat-s5p/dev-fimc2.c - * - * Copyright (c) 2010 Samsung Electronics - * - * Base S5P FIMC2 resource and device definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <mach/map.h> - -static struct resource s5p_fimc2_resource[] = { - [0] = { - .start = S5P_PA_FIMC2, - .end = S5P_PA_FIMC2 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_FIMC2, - .end = IRQ_FIMC2, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 s5p_fimc2_dma_mask = DMA_BIT_MASK(32); - -struct platform_device s5p_device_fimc2 = { - .name = "s5p-fimc", - .id = 2, - .num_resources = ARRAY_SIZE(s5p_fimc2_resource), - .resource = s5p_fimc2_resource, - .dev = { - .dma_mask = &s5p_fimc2_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/plat-s5p/dev-fimc3.c b/arch/arm/plat-s5p/dev-fimc3.c deleted file mode 100644 index ef31beca386c..000000000000 --- a/arch/arm/plat-s5p/dev-fimc3.c +++ /dev/null @@ -1,43 +0,0 @@ -/* linux/arch/arm/plat-s5p/dev-fimc3.c - * - * Copyright (c) 2010 Samsung Electronics - * - * Base S5P FIMC3 resource and device definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/ioport.h> -#include <mach/map.h> - -static struct resource s5p_fimc3_resource[] = { - [0] = { - .start = S5P_PA_FIMC3, - .end = S5P_PA_FIMC3 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_FIMC3, - .end = IRQ_FIMC3, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 s5p_fimc3_dma_mask = DMA_BIT_MASK(32); - -struct platform_device s5p_device_fimc3 = { - .name = "s5p-fimc", - .id = 3, - .num_resources = ARRAY_SIZE(s5p_fimc3_resource), - .resource = s5p_fimc3_resource, - .dev = { - .dma_mask = &s5p_fimc3_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/plat-s5p/dev-fimd0.c b/arch/arm/plat-s5p/dev-fimd0.c deleted file mode 100644 index f728bb5abcef..000000000000 --- a/arch/arm/plat-s5p/dev-fimd0.c +++ /dev/null @@ -1,67 +0,0 @@ -/* linux/arch/arm/plat-s5p/dev-fimd0.c - * - * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Core file for Samsung Display Controller (FIMD) driver - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> -#include <linux/fb.h> -#include <linux/gfp.h> -#include <linux/dma-mapping.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/fb.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s5p_fimd0_resource[] = { - [0] = { - .start = S5P_PA_FIMD0, - .end = S5P_PA_FIMD0 + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_FIMD0_VSYNC, - .end = IRQ_FIMD0_VSYNC, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_FIMD0_FIFO, - .end = IRQ_FIMD0_FIFO, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = IRQ_FIMD0_SYSTEM, - .end = IRQ_FIMD0_SYSTEM, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 fimd0_dmamask = DMA_BIT_MASK(32); - -struct platform_device s5p_device_fimd0 = { - .name = "s5p-fb", - .id = 0, - .num_resources = ARRAY_SIZE(s5p_fimd0_resource), - .resource = s5p_fimd0_resource, - .dev = { - .dma_mask = &fimd0_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd) -{ - s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata), - &s5p_device_fimd0); -} diff --git a/arch/arm/plat-s5p/dev-mfc.c b/arch/arm/plat-s5p/dev-mfc.c index 94226a0010f7..a30d36b7f61b 100644 --- a/arch/arm/plat-s5p/dev-mfc.c +++ b/arch/arm/plat-s5p/dev-mfc.c @@ -22,56 +22,6 @@ #include <plat/irqs.h> #include <plat/mfc.h> -static struct resource s5p_mfc_resource[] = { - [0] = { - .start = S5P_PA_MFC, - .end = S5P_PA_MFC + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_MFC, - .end = IRQ_MFC, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device s5p_device_mfc = { - .name = "s5p-mfc", - .id = -1, - .num_resources = ARRAY_SIZE(s5p_mfc_resource), - .resource = s5p_mfc_resource, -}; - -/* - * MFC hardware has 2 memory interfaces which are modelled as two separate - * platform devices to let dma-mapping distinguish between them. - * - * MFC parent device (s5p_device_mfc) must be registered before memory - * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r). - */ - -static u64 s5p_mfc_dma_mask = DMA_BIT_MASK(32); - -struct platform_device s5p_device_mfc_l = { - .name = "s5p-mfc-l", - .id = -1, - .dev = { - .parent = &s5p_device_mfc.dev, - .dma_mask = &s5p_mfc_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device s5p_device_mfc_r = { - .name = "s5p-mfc-r", - .id = -1, - .dev = { - .parent = &s5p_device_mfc.dev, - .dma_mask = &s5p_mfc_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - struct s5p_mfc_reserved_mem { phys_addr_t base; unsigned long size; diff --git a/arch/arm/plat-s5p/dev-onenand.c b/arch/arm/plat-s5p/dev-onenand.c deleted file mode 100644 index 20336c8f2479..000000000000 --- a/arch/arm/plat-s5p/dev-onenand.c +++ /dev/null @@ -1,45 +0,0 @@ -/* linux/arch/arm/plat-s5p/dev-onenand.c - * - * Copyright 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright (c) 2008-2010 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * S5P series device definition for OneNAND devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -static struct resource s5p_onenand_resources[] = { - [0] = { - .start = S5P_PA_ONENAND, - .end = S5P_PA_ONENAND + SZ_128K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S5P_PA_ONENAND_DMA, - .end = S5P_PA_ONENAND_DMA + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_ONENAND_AUDI, - .end = IRQ_ONENAND_AUDI, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s5p_device_onenand = { - .name = "s5pc110-onenand", - .id = -1, - .num_resources = ARRAY_SIZE(s5p_onenand_resources), - .resource = s5p_onenand_resources, -}; diff --git a/arch/arm/plat-s5p/dev-pmu.c b/arch/arm/plat-s5p/dev-pmu.c deleted file mode 100644 index a08576da72b0..000000000000 --- a/arch/arm/plat-s5p/dev-pmu.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * linux/arch/arm/plat-s5p/dev-pmu.c - * - * Copyright (C) 2010 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim <jy0922.shim@samsung.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include <linux/platform_device.h> -#include <asm/pmu.h> -#include <mach/irqs.h> - -static struct resource s5p_pmu_resource = { - .start = IRQ_PMU, - .end = IRQ_PMU, - .flags = IORESOURCE_IRQ, -}; - -struct platform_device s5p_device_pmu = { - .name = "arm-pmu", - .id = ARM_PMU_DEVICE_CPU, - .num_resources = 1, - .resource = &s5p_pmu_resource, -}; - -static int __init s5p_pmu_init(void) -{ - platform_device_register(&s5p_device_pmu); - return 0; -} -arch_initcall(s5p_pmu_init); diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index c65eb791d1bb..1fdfaa4599ce 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c @@ -37,7 +37,7 @@ struct s5p_gpioint_bank { int start; int nr_groups; int irq; - struct s3c_gpio_chip **chips; + struct samsung_gpio_chip **chips; void (*handler)(unsigned int, struct irq_desc *); }; @@ -87,7 +87,7 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) chained_irq_enter(chip, desc); for (group = 0; group < bank->nr_groups; group++) { - struct s3c_gpio_chip *chip = bank->chips[group]; + struct samsung_gpio_chip *chip = bank->chips[group]; if (!chip) continue; @@ -110,7 +110,7 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) chained_irq_exit(chip, desc); } -static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) +static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip) { static int used_gpioint_groups = 0; int group = chip->group; @@ -131,7 +131,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) return -EINVAL; if (!bank->handler) { - bank->chips = kzalloc(sizeof(struct s3c_gpio_chip *) * + bank->chips = kzalloc(sizeof(struct samsung_gpio_chip *) * bank->nr_groups, GFP_KERNEL); if (!bank->chips) return -ENOMEM; @@ -174,7 +174,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) int __init s5p_register_gpio_interrupt(int pin) { - struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin); + struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin); int offset, group; int ret; diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/plat-s5p/sleep.S index 0984078f1eba..0fd591bfc9fd 100644 --- a/arch/arm/mach-exynos4/sleep.S +++ b/arch/arm/plat-s5p/sleep.S @@ -1,15 +1,11 @@ -/* linux/arch/arm/mach-exynos4/sleep.S +/* linux/arch/arm/plat-s5p/sleep.S * * Copyright (c) 2011 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * EXYNOS4210 power Manager (Suspend-To-RAM) support - * Based on S3C2410 sleep code by: - * Ben Dooks, (c) 2004 Simtec Electronics - * - * Based on PXA/SA1100 sleep code by: - * Nicolas Pitre, (c) 2002 Monta Vista Software Inc - * Cliff Brake, (c) 2001 + * Common S5P Sleep Code + * Based on S3C64XX sleep code by: + * Ben Dooks, (c) 2008 Simtec Electronics * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,7 +24,6 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#include <asm/memory.h> .text diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 7a96198e3a78..313eb26cfa62 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -74,39 +74,12 @@ config SAMSUNG_GPIOLIB_4BIT configuration. GPIOlib shall be compiled only for S3C64XX and S5P series of processors. -config S3C_GPIO_CFG_S3C24XX - bool - help - Internal configuration to enable S3C24XX style GPIO configuration - functions. - config S3C_GPIO_CFG_S3C64XX bool help Internal configuration to enable S3C64XX style GPIO configuration functions. -config S3C_GPIO_PULL_UPDOWN - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_PULL_S3C2443 - bool - select S3C_GPIO_PULL_UPDOWN - help - Internal configuration to enable the correct GPIO pull helper for S3C2443-style GPIO - -config S3C_GPIO_PULL_DOWN - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_PULL_UP - bool - help - Internal configuration to enable the correct GPIO pull helper - config S5P_GPIO_DRVSTR bool help diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 3dd5dbad55c6..6012366f33cb 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -1,4 +1,4 @@ -# arch/arm/plat-s3c64xx/Makefile +# arch/arm/plat-samsung/Makefile # # Copyright 2009 Simtec Electronics # @@ -15,9 +15,6 @@ obj-y += init.o cpu.o obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o obj-y += clock.o obj-y += pwm-clock.o -obj-y += gpio.o -obj-y += gpio-config.o -obj-y += dev-asocdma.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o @@ -31,33 +28,9 @@ obj-$(CONFIG_S3C_ADC) += adc.o obj-y += platformdata.o -obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o -obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o -obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o -obj-$(CONFIG_S3C_DEV_HSMMC3) += dev-hsmmc3.o -obj-$(CONFIG_S3C_DEV_HWMON) += dev-hwmon.o -obj-y += dev-i2c0.o -obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o -obj-$(CONFIG_S3C_DEV_I2C2) += dev-i2c2.o -obj-$(CONFIG_S3C_DEV_I2C3) += dev-i2c3.o -obj-$(CONFIG_S3C_DEV_I2C4) += dev-i2c4.o -obj-$(CONFIG_S3C_DEV_I2C5) += dev-i2c5.o -obj-$(CONFIG_S3C_DEV_I2C6) += dev-i2c6.o -obj-$(CONFIG_S3C_DEV_I2C7) += dev-i2c7.o -obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o +obj-y += devs.o obj-y += dev-uart.o -obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o -obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o -obj-$(CONFIG_S3C_DEV_WDT) += dev-wdt.o -obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o -obj-$(CONFIG_S3C_DEV_ONENAND) += dev-onenand.o -obj-$(CONFIG_S3C_DEV_RTC) += dev-rtc.o - -obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o -obj-$(CONFIG_SAMSUNG_DEV_IDE) += dev-ide.o -obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o -obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) += dev-keypad.o -obj-$(CONFIG_SAMSUNG_DEV_PWM) += dev-pwm.o + obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o # DMA support diff --git a/arch/arm/plat-samsung/dev-adc.c b/arch/arm/plat-samsung/dev-adc.c deleted file mode 100644 index 9d903d4095ed..000000000000 --- a/arch/arm/plat-samsung/dev-adc.c +++ /dev/null @@ -1,46 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-adc.c - * - * Copyright 2010 Maurus Cuelenaere - * - * S3C64xx series device definition for ADC device - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/adc.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_adc_resource[] = { - [0] = { - .start = SAMSUNG_PA_ADC, - .end = SAMSUNG_PA_ADC + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TC, - .end = IRQ_TC, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_ADC, - .end = IRQ_ADC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_adc = { - .name = "samsung-adc", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_adc_resource), - .resource = s3c_adc_resource, -}; diff --git a/arch/arm/plat-samsung/dev-asocdma.c b/arch/arm/plat-samsung/dev-asocdma.c deleted file mode 100644 index 97e35d3c064d..000000000000 --- a/arch/arm/plat-samsung/dev-asocdma.c +++ /dev/null @@ -1,35 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-asocdma.c - * - * Copyright (c) 2010 Samsung Electronics Co. Ltd - * Jaswinder Singh <jassi.brar@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <plat/devs.h> - -static u64 audio_dmamask = DMA_BIT_MASK(32); - -struct platform_device samsung_asoc_dma = { - .name = "samsung-audio", - .id = -1, - .dev = { - .dma_mask = &audio_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - } -}; -EXPORT_SYMBOL(samsung_asoc_dma); - -struct platform_device samsung_asoc_idma = { - .name = "samsung-idma", - .id = -1, - .dev = { - .dma_mask = &audio_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - } -}; -EXPORT_SYMBOL(samsung_asoc_idma); diff --git a/arch/arm/plat-samsung/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c deleted file mode 100644 index 49a1362fd25b..000000000000 --- a/arch/arm/plat-samsung/dev-fb.c +++ /dev/null @@ -1,63 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-fb.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for framebuffer device - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> -#include <linux/fb.h> -#include <linux/gfp.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/fb.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_fb_resource[] = { - [0] = { - .start = S3C_PA_FB, - .end = S3C_PA_FB + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_LCD_VSYNC, - .end = IRQ_LCD_VSYNC, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_LCD_FIFO, - .end = IRQ_LCD_FIFO, - .flags = IORESOURCE_IRQ, - }, - [3] = { - .start = IRQ_LCD_SYSTEM, - .end = IRQ_LCD_SYSTEM, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_fb = { - .name = "s3c-fb", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_fb_resource), - .resource = s3c_fb_resource, - .dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask, - .dev.coherent_dma_mask = 0xffffffffUL, -}; - -void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd) -{ - s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata), - &s3c_device_fb); -} diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c deleted file mode 100644 index 06825c4276de..000000000000 --- a/arch/arm/plat-samsung/dev-hsmmc.c +++ /dev/null @@ -1,62 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-hsmmc.c - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for hsmmc devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mmc/host.h> - -#include <mach/map.h> -#include <plat/sdhci.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -#define S3C_SZ_HSMMC (0x1000) - -static struct resource s3c_hsmmc_resource[] = { - [0] = { - .start = S3C_PA_HSMMC0, - .end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_HSMMC0, - .end = IRQ_HSMMC0, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL; - -struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = { - .max_width = 4, - .host_caps = (MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), - .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, -}; - -struct platform_device s3c_device_hsmmc0 = { - .name = "s3c-sdhci", - .id = 0, - .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), - .resource = s3c_hsmmc_resource, - .dev = { - .dma_mask = &s3c_device_hsmmc_dmamask, - .coherent_dma_mask = 0xffffffffUL, - .platform_data = &s3c_hsmmc0_def_platdata, - }, -}; - -void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) -{ - s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata); -} diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c deleted file mode 100644 index 4524ef440010..000000000000 --- a/arch/arm/plat-samsung/dev-hsmmc1.c +++ /dev/null @@ -1,62 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-hsmmc1.c - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for hsmmc device 1 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mmc/host.h> - -#include <mach/map.h> -#include <plat/sdhci.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -#define S3C_SZ_HSMMC (0x1000) - -static struct resource s3c_hsmmc1_resource[] = { - [0] = { - .start = S3C_PA_HSMMC1, - .end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_HSMMC1, - .end = IRQ_HSMMC1, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL; - -struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = { - .max_width = 4, - .host_caps = (MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), - .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, -}; - -struct platform_device s3c_device_hsmmc1 = { - .name = "s3c-sdhci", - .id = 1, - .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource), - .resource = s3c_hsmmc1_resource, - .dev = { - .dma_mask = &s3c_device_hsmmc1_dmamask, - .coherent_dma_mask = 0xffffffffUL, - .platform_data = &s3c_hsmmc1_def_platdata, - }, -}; - -void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) -{ - s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata); -} diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c deleted file mode 100644 index 9cede9615e48..000000000000 --- a/arch/arm/plat-samsung/dev-hsmmc2.c +++ /dev/null @@ -1,63 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-hsmmc2.c - * - * Copyright (c) 2009 Samsung Electronics - * Copyright (c) 2009 Maurus Cuelenaere - * - * Based on arch/arm/plat-s3c/dev-hsmmc1.c - * original file Copyright (c) 2008 Simtec Electronics - * - * S3C series device definition for hsmmc device 2 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mmc/host.h> - -#include <mach/map.h> -#include <plat/sdhci.h> -#include <plat/devs.h> - -#define S3C_SZ_HSMMC (0x1000) - -static struct resource s3c_hsmmc2_resource[] = { - [0] = { - .start = S3C_PA_HSMMC2, - .end = S3C_PA_HSMMC2 + S3C_SZ_HSMMC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_HSMMC2, - .end = IRQ_HSMMC2, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_device_hsmmc2_dmamask = 0xffffffffUL; - -struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = { - .max_width = 4, - .host_caps = (MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), - .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, -}; - -struct platform_device s3c_device_hsmmc2 = { - .name = "s3c-sdhci", - .id = 2, - .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource), - .resource = s3c_hsmmc2_resource, - .dev = { - .dma_mask = &s3c_device_hsmmc2_dmamask, - .coherent_dma_mask = 0xffffffffUL, - .platform_data = &s3c_hsmmc2_def_platdata, - }, -}; - -void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) -{ - s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata); -} diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c deleted file mode 100644 index 0358ef4a8f66..000000000000 --- a/arch/arm/plat-samsung/dev-hsmmc3.c +++ /dev/null @@ -1,66 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-hsmmc3.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Based on arch/arm/plat-samsung/dev-hsmmc1.c - * - * Samsung device definition for hsmmc device 3 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mmc/host.h> - -#include <mach/map.h> -#include <plat/sdhci.h> -#include <plat/devs.h> - -#define S3C_SZ_HSMMC (0x1000) - -static struct resource s3c_hsmmc3_resource[] = { - [0] = { - .start = S3C_PA_HSMMC3, - .end = S3C_PA_HSMMC3 + S3C_SZ_HSMMC - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_HSMMC3, - .end = IRQ_HSMMC3, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_device_hsmmc3_dmamask = 0xffffffffUL; - -struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = { - .max_width = 4, - .host_caps = (MMC_CAP_4_BIT_DATA | - MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), - .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, -}; - -struct platform_device s3c_device_hsmmc3 = { - .name = "s3c-sdhci", - .id = 3, - .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource), - .resource = s3c_hsmmc3_resource, - .dev = { - .dma_mask = &s3c_device_hsmmc3_dmamask, - .coherent_dma_mask = 0xffffffffUL, - .platform_data = &s3c_hsmmc3_def_platdata, - }, -}; - -void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd) -{ - s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata); -} diff --git a/arch/arm/plat-samsung/dev-hwmon.c b/arch/arm/plat-samsung/dev-hwmon.c deleted file mode 100644 index c91a79ce8f39..000000000000 --- a/arch/arm/plat-samsung/dev-hwmon.c +++ /dev/null @@ -1,32 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-hwmon.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Adapted for HWMON by Maurus Cuelenaere - * - * Samsung series device definition for HWMON - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <plat/devs.h> -#include <plat/hwmon.h> - -struct platform_device s3c_device_hwmon = { - .name = "s3c-hwmon", - .id = -1, - .dev.parent = &s3c_device_adc.dev, -}; - -void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd) -{ - s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata), - &s3c_device_hwmon); -} diff --git a/arch/arm/plat-samsung/dev-i2c0.c b/arch/arm/plat-samsung/dev-i2c0.c deleted file mode 100644 index f8251f5098bd..000000000000 --- a/arch/arm/plat-samsung/dev-i2c0.c +++ /dev/null @@ -1,70 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-i2c0.c - * - * Copyright 2008-2009 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for i2c device 0 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/regs-iic.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C_PA_IIC, - .end = S3C_PA_IIC + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC, - .end = IRQ_IIC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_i2c0 = { - .name = "s3c2410-i2c", -#ifdef CONFIG_S3C_DEV_I2C1 - .id = 0, -#else - .id = -1, -#endif - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -struct s3c2410_platform_i2c default_i2c_data __initdata = { - .flags = 0, - .slave_addr = 0x10, - .frequency = 100*1000, - .sda_delay = 100, -}; - -void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) -{ - struct s3c2410_platform_i2c *npd; - - if (!pd) - pd = &default_i2c_data; - - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c0); - - if (!npd->cfg_gpio) - npd->cfg_gpio = s3c_i2c0_cfg_gpio; -} diff --git a/arch/arm/plat-samsung/dev-i2c1.c b/arch/arm/plat-samsung/dev-i2c1.c deleted file mode 100644 index 3b7c7bec1cf9..000000000000 --- a/arch/arm/plat-samsung/dev-i2c1.c +++ /dev/null @@ -1,61 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-i2c1.c - * - * Copyright 2008-2009 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for i2c device 1 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/regs-iic.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C_PA_IIC1, - .end = S3C_PA_IIC1 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC1, - .end = IRQ_IIC1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_i2c1 = { - .name = "s3c2410-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) -{ - struct s3c2410_platform_i2c *npd; - - if (!pd) { - pd = &default_i2c_data; - pd->bus_num = 1; - } - - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c1); - - if (!npd->cfg_gpio) - npd->cfg_gpio = s3c_i2c1_cfg_gpio; -} diff --git a/arch/arm/plat-samsung/dev-i2c2.c b/arch/arm/plat-samsung/dev-i2c2.c deleted file mode 100644 index 07e9fd0b1b8b..000000000000 --- a/arch/arm/plat-samsung/dev-i2c2.c +++ /dev/null @@ -1,62 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-i2c2.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S3C series device definition for i2c device 2 - * - * Based on plat-samsung/dev-i2c0.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/regs-iic.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C_PA_IIC2, - .end = S3C_PA_IIC2 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC2, - .end = IRQ_IIC2, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_i2c2 = { - .name = "s3c2410-i2c", - .id = 2, - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd) -{ - struct s3c2410_platform_i2c *npd; - - if (!pd) { - pd = &default_i2c_data; - pd->bus_num = 2; - } - - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c2); - - if (!npd->cfg_gpio) - npd->cfg_gpio = s3c_i2c2_cfg_gpio; -} diff --git a/arch/arm/plat-samsung/dev-i2c3.c b/arch/arm/plat-samsung/dev-i2c3.c deleted file mode 100644 index d48efa93c6e7..000000000000 --- a/arch/arm/plat-samsung/dev-i2c3.c +++ /dev/null @@ -1,60 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-i2c3.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5P series device definition for i2c device 3 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/regs-iic.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C_PA_IIC3, - .end = S3C_PA_IIC3 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC3, - .end = IRQ_IIC3, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_i2c3 = { - .name = "s3c2440-i2c", - .id = 3, - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd) -{ - struct s3c2410_platform_i2c *npd; - - if (!pd) { - pd = &default_i2c_data; - pd->bus_num = 3; - } - - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c3); - - if (!npd->cfg_gpio) - npd->cfg_gpio = s3c_i2c3_cfg_gpio; -} diff --git a/arch/arm/plat-samsung/dev-i2c4.c b/arch/arm/plat-samsung/dev-i2c4.c deleted file mode 100644 index 07e26444efe6..000000000000 --- a/arch/arm/plat-samsung/dev-i2c4.c +++ /dev/null @@ -1,60 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-i2c4.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5P series device definition for i2c device 3 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/regs-iic.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C_PA_IIC4, - .end = S3C_PA_IIC4 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC4, - .end = IRQ_IIC4, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_i2c4 = { - .name = "s3c2440-i2c", - .id = 4, - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd) -{ - struct s3c2410_platform_i2c *npd; - - if (!pd) { - pd = &default_i2c_data; - pd->bus_num = 4; - } - - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c4); - - if (!npd->cfg_gpio) - npd->cfg_gpio = s3c_i2c4_cfg_gpio; -} diff --git a/arch/arm/plat-samsung/dev-i2c5.c b/arch/arm/plat-samsung/dev-i2c5.c deleted file mode 100644 index f49655784563..000000000000 --- a/arch/arm/plat-samsung/dev-i2c5.c +++ /dev/null @@ -1,60 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-i2c3.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5P series device definition for i2c device 3 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/regs-iic.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C_PA_IIC5, - .end = S3C_PA_IIC5 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC5, - .end = IRQ_IIC5, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_i2c5 = { - .name = "s3c2440-i2c", - .id = 5, - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd) -{ - struct s3c2410_platform_i2c *npd; - - if (!pd) { - pd = &default_i2c_data; - pd->bus_num = 5; - } - - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c5); - - if (!npd->cfg_gpio) - npd->cfg_gpio = s3c_i2c5_cfg_gpio; -} diff --git a/arch/arm/plat-samsung/dev-i2c6.c b/arch/arm/plat-samsung/dev-i2c6.c deleted file mode 100644 index 141d799944e2..000000000000 --- a/arch/arm/plat-samsung/dev-i2c6.c +++ /dev/null @@ -1,60 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-i2c6.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5P series device definition for i2c device 6 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/regs-iic.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C_PA_IIC6, - .end = S3C_PA_IIC6 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC6, - .end = IRQ_IIC6, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_i2c6 = { - .name = "s3c2440-i2c", - .id = 6, - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd) -{ - struct s3c2410_platform_i2c *npd; - - if (!pd) { - pd = &default_i2c_data; - pd->bus_num = 6; - } - - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c6); - - if (!npd->cfg_gpio) - npd->cfg_gpio = s3c_i2c6_cfg_gpio; -} diff --git a/arch/arm/plat-samsung/dev-i2c7.c b/arch/arm/plat-samsung/dev-i2c7.c deleted file mode 100644 index 9dddcd1665b5..000000000000 --- a/arch/arm/plat-samsung/dev-i2c7.c +++ /dev/null @@ -1,60 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-i2c7.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * S5P series device definition for i2c device 7 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/regs-iic.h> -#include <plat/iic.h> -#include <plat/devs.h> -#include <plat/cpu.h> - -static struct resource s3c_i2c_resource[] = { - [0] = { - .start = S3C_PA_IIC7, - .end = S3C_PA_IIC7 + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IIC7, - .end = IRQ_IIC7, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_i2c7 = { - .name = "s3c2440-i2c", - .id = 7, - .num_resources = ARRAY_SIZE(s3c_i2c_resource), - .resource = s3c_i2c_resource, -}; - -void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd) -{ - struct s3c2410_platform_i2c *npd; - - if (!pd) { - pd = &default_i2c_data; - pd->bus_num = 7; - } - - npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), - &s3c_device_i2c7); - - if (!npd->cfg_gpio) - npd->cfg_gpio = s3c_i2c7_cfg_gpio; -} diff --git a/arch/arm/plat-samsung/dev-ide.c b/arch/arm/plat-samsung/dev-ide.c deleted file mode 100644 index b497982795a7..000000000000 --- a/arch/arm/plat-samsung/dev-ide.c +++ /dev/null @@ -1,44 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-ide.c - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Samsung CF-ATA device definition. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> - -#include <mach/map.h> -#include <plat/ata.h> -#include <plat/devs.h> - -static struct resource s3c_cfcon_resource[] = { - [0] = { - .start = SAMSUNG_PA_CFCON, - .end = SAMSUNG_PA_CFCON + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CFCON, - .end = IRQ_CFCON, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_cfcon = { - .id = 0, - .num_resources = ARRAY_SIZE(s3c_cfcon_resource), - .resource = s3c_cfcon_resource, -}; - -void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata) -{ - s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata), - &s3c_device_cfcon); -} diff --git a/arch/arm/plat-samsung/dev-keypad.c b/arch/arm/plat-samsung/dev-keypad.c deleted file mode 100644 index 677c2d731b65..000000000000 --- a/arch/arm/plat-samsung/dev-keypad.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * linux/arch/arm/plat-samsung/dev-keypad.c - * - * Copyright (C) 2010 Samsung Electronics Co.Ltd - * Author: Joonyoung Shim <jy0922.shim@samsung.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#include <linux/platform_device.h> -#include <mach/irqs.h> -#include <mach/map.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/keypad.h> - -static struct resource samsung_keypad_resources[] = { - [0] = { - .start = SAMSUNG_PA_KEYPAD, - .end = SAMSUNG_PA_KEYPAD + 0x20 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_KEYPAD, - .end = IRQ_KEYPAD, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device samsung_device_keypad = { - .name = "samsung-keypad", - .id = -1, - .num_resources = ARRAY_SIZE(samsung_keypad_resources), - .resource = samsung_keypad_resources, -}; - -void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd) -{ - struct samsung_keypad_platdata *npd; - - npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata), - &samsung_device_keypad); - - if (!npd->cfg_gpio) - npd->cfg_gpio = samsung_keypad_cfg_gpio; -} diff --git a/arch/arm/plat-samsung/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c deleted file mode 100644 index b8e30ec6ac26..000000000000 --- a/arch/arm/plat-samsung/dev-nand.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * S3C series device definition for nand device - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> - -#include <mach/map.h> -#include <plat/devs.h> -#include <plat/nand.h> - -static struct resource s3c_nand_resource[] = { - [0] = { - .start = S3C_PA_NAND, - .end = S3C_PA_NAND + SZ_1M, - .flags = IORESOURCE_MEM, - } -}; - -struct platform_device s3c_device_nand = { - .name = "s3c2410-nand", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_nand_resource), - .resource = s3c_nand_resource, -}; - -EXPORT_SYMBOL(s3c_device_nand); - -/** - * s3c_nand_copy_set() - copy nand set data - * @set: The new structure, directly copied from the old. - * - * Copy all the fields from the NAND set field from what is probably __initdata - * to new kernel memory. The code returns 0 if the copy happened correctly or - * an error code for the calling function to display. - * - * Note, we currently do not try and look to see if we've already copied the - * data in a previous set. - */ -static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set) -{ - void *ptr; - int size; - - size = sizeof(struct mtd_partition) * set->nr_partitions; - if (size) { - ptr = kmemdup(set->partitions, size, GFP_KERNEL); - set->partitions = ptr; - - if (!ptr) - return -ENOMEM; - } - - if (set->nr_map && set->nr_chips) { - size = sizeof(int) * set->nr_chips; - ptr = kmemdup(set->nr_map, size, GFP_KERNEL); - set->nr_map = ptr; - - if (!ptr) - return -ENOMEM; - } - - if (set->ecc_layout) { - ptr = kmemdup(set->ecc_layout, - sizeof(struct nand_ecclayout), GFP_KERNEL); - set->ecc_layout = ptr; - - if (!ptr) - return -ENOMEM; - } - - return 0; -} - -void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand) -{ - struct s3c2410_platform_nand *npd; - int size; - int ret; - - /* note, if we get a failure in allocation, we simply drop out of the - * function. If there is so little memory available at initialisation - * time then there is little chance the system is going to run. - */ - - npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand), - &s3c_device_nand); - if (!npd) - return; - - /* now see if we need to copy any of the nand set data */ - - size = sizeof(struct s3c2410_nand_set) * npd->nr_sets; - if (size) { - struct s3c2410_nand_set *from = npd->sets; - struct s3c2410_nand_set *to; - int i; - - to = kmemdup(from, size, GFP_KERNEL); - npd->sets = to; /* set, even if we failed */ - - if (!to) { - printk(KERN_ERR "%s: no memory for sets\n", __func__); - return; - } - - for (i = 0; i < npd->nr_sets; i++) { - ret = s3c_nand_copy_set(to); - if (ret) { - printk(KERN_ERR "%s: failed to copy set %d\n", - __func__, i); - return; - } - to++; - } - } -} diff --git a/arch/arm/plat-samsung/dev-onenand.c b/arch/arm/plat-samsung/dev-onenand.c deleted file mode 100644 index f54ae71f0cd2..000000000000 --- a/arch/arm/plat-samsung/dev-onenand.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * linux/arch/arm/plat-samsung/dev-onenand.c - * - * Copyright (c) 2008-2010 Samsung Electronics - * Kyungmin Park <kyungmin.park@samsung.com> - * - * S3C64XX/S5PC100 series device definition for OneNAND devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -static struct resource s3c_onenand_resources[] = { - [0] = { - .start = S3C_PA_ONENAND, - .end = S3C_PA_ONENAND + 0x400 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = S3C_PA_ONENAND_BUF, - .end = S3C_PA_ONENAND_BUF + S3C_SZ_ONENAND_BUF - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = IRQ_ONENAND, - .end = IRQ_ONENAND, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_onenand = { - .name = "samsung-onenand", - .id = 0, - .num_resources = ARRAY_SIZE(s3c_onenand_resources), - .resource = s3c_onenand_resources, -}; diff --git a/arch/arm/plat-samsung/dev-pwm.c b/arch/arm/plat-samsung/dev-pwm.c deleted file mode 100644 index dab47b0e1900..000000000000 --- a/arch/arm/plat-samsung/dev-pwm.c +++ /dev/null @@ -1,53 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-pwm.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright (c) 2007 Ben Dooks - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> - * - * S3C series device definition for the PWM timer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> - -#include <plat/devs.h> - -#define TIMER_RESOURCE_SIZE (1) - -#define TIMER_RESOURCE(_tmr, _irq) \ - (struct resource [TIMER_RESOURCE_SIZE]) { \ - [0] = { \ - .start = _irq, \ - .end = _irq, \ - .flags = IORESOURCE_IRQ \ - } \ - } - -#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ - .name = "s3c24xx-pwm", \ - .id = _tmr_no, \ - .num_resources = TIMER_RESOURCE_SIZE, \ - .resource = TIMER_RESOURCE(_tmr_no, _irq), \ - -/* - * since we already have an static mapping for the timer, - * we do not bother setting any IO resource for the base. - */ - -struct platform_device s3c_device_timer[] = { - [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, - [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, - [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, - [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, - [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, -}; -EXPORT_SYMBOL(s3c_device_timer); diff --git a/arch/arm/plat-samsung/dev-rtc.c b/arch/arm/plat-samsung/dev-rtc.c deleted file mode 100644 index bf4e2267333c..000000000000 --- a/arch/arm/plat-samsung/dev-rtc.c +++ /dev/null @@ -1,43 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-rtc.c - * - * Copyright 2009 by Maurus Cuelenaere <mcuelenaere@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/devs.h> - -static struct resource s3c_rtc_resource[] = { - [0] = { - .start = S3C_PA_RTC, - .end = S3C_PA_RTC + 0xff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_RTC_ALARM, - .end = IRQ_RTC_ALARM, - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = IRQ_RTC_TIC, - .end = IRQ_RTC_TIC, - .flags = IORESOURCE_IRQ - } -}; - -struct platform_device s3c_device_rtc = { - .name = "s3c64xx-rtc", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_rtc_resource), - .resource = s3c_rtc_resource, -}; -EXPORT_SYMBOL(s3c_device_rtc); diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c deleted file mode 100644 index 5f3d46a9bd88..000000000000 --- a/arch/arm/plat-samsung/dev-ts.c +++ /dev/null @@ -1,59 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/dev-ts.c - * - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> - * - * Adapted by Maurus Cuelenaere for s3c64xx - * - * S3C64XX series device definition for touchscreen device - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/devs.h> -#include <plat/ts.h> - -static struct resource s3c_ts_resource[] = { - [0] = { - .start = SAMSUNG_PA_ADC, - .end = SAMSUNG_PA_ADC + SZ_256 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_TC, - .end = IRQ_TC, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device s3c_device_ts = { - .name = "s3c64xx-ts", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_ts_resource), - .resource = s3c_ts_resource, -}; - -static struct s3c2410_ts_mach_info default_ts_data __initdata = { - .delay = 10000, - .presc = 49, - .oversampling_shift = 2, -}; - -void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd) -{ - if (!pd) - pd = &default_ts_data; - - s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info), - &s3c_device_ts); -} diff --git a/arch/arm/plat-samsung/dev-usb-hsotg.c b/arch/arm/plat-samsung/dev-usb-hsotg.c deleted file mode 100644 index 33a844ab6917..000000000000 --- a/arch/arm/plat-samsung/dev-usb-hsotg.c +++ /dev/null @@ -1,48 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-usb-hsotg.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for USB high-speed UDC/OtG block - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/devs.h> - -static struct resource s3c_usb_hsotg_resources[] = { - [0] = { - .start = S3C_PA_USB_HSOTG, - .end = S3C_PA_USB_HSOTG + 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_OTG, - .end = IRQ_OTG, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 s3c_hsotg_dmamask = DMA_BIT_MASK(32); - -struct platform_device s3c_device_usb_hsotg = { - .name = "s3c-hsotg", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources), - .resource = s3c_usb_hsotg_resources, - .dev = { - .dma_mask = &s3c_hsotg_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; diff --git a/arch/arm/plat-samsung/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c deleted file mode 100644 index 33fbaa967700..000000000000 --- a/arch/arm/plat-samsung/dev-usb.c +++ /dev/null @@ -1,65 +0,0 @@ -/* linux/arch/arm/plat-s3c/dev-usb.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series device definition for USB host - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/gfp.h> -#include <linux/kernel.h> -#include <linux/string.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/devs.h> -#include <plat/usb-control.h> - -static struct resource s3c_usb_resource[] = { - [0] = { - .start = S3C_PA_USBHOST, - .end = S3C_PA_USBHOST + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_USBH, - .end = IRQ_USBH, - .flags = IORESOURCE_IRQ, - } -}; - -static u64 s3c_device_usb_dmamask = 0xffffffffUL; - -struct platform_device s3c_device_ohci = { - .name = "s3c2410-ohci", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_usb_resource), - .resource = s3c_usb_resource, - .dev = { - .dma_mask = &s3c_device_usb_dmamask, - .coherent_dma_mask = 0xffffffffUL - } -}; - -EXPORT_SYMBOL(s3c_device_ohci); - -/** - * s3c_ohci_set_platdata - initialise OHCI device platform data - * @info: The platform data. - * - * This call copies the @info passed in and sets the device .platform_data - * field to that copy. The @info is copied so that the original can be marked - * __initdata. - */ -void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info) -{ - s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info), - &s3c_device_ohci); -} diff --git a/arch/arm/plat-samsung/dev-wdt.c b/arch/arm/plat-samsung/dev-wdt.c deleted file mode 100644 index 019b5b8cf14c..000000000000 --- a/arch/arm/plat-samsung/dev-wdt.c +++ /dev/null @@ -1,40 +0,0 @@ -/* linux/arch/arm/plat-samsung/dev-wdt.c - * - * Copyright (c) 2004 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C series device definition for the watchdog timer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/platform_device.h> - -#include <mach/irqs.h> -#include <mach/map.h> - -#include <plat/devs.h> - -static struct resource s3c_wdt_resource[] = { - [0] = { - .start = S3C_PA_WDT, - .end = S3C_PA_WDT + SZ_1K, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_WDT, - .end = IRQ_WDT, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device s3c_device_wdt = { - .name = "s3c2410-wdt", - .id = -1, - .num_resources = ARRAY_SIZE(s3c_wdt_resource), - .resource = s3c_wdt_resource, -}; -EXPORT_SYMBOL(s3c_device_wdt); diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c new file mode 100644 index 000000000000..4ca8b571f971 --- /dev/null +++ b/arch/arm/plat-samsung/devs.c @@ -0,0 +1,1463 @@ +/* linux/arch/arm/plat-samsung/devs.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Base SAMSUNG platform device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/dma-mapping.h> +#include <linux/fb.h> +#include <linux/gfp.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/onenand.h> +#include <linux/mtd/partitions.h> +#include <linux/mmc/host.h> +#include <linux/ioport.h> + +#include <asm/irq.h> +#include <asm/pmu.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <mach/hardware.h> +#include <mach/dma.h> +#include <mach/irqs.h> +#include <mach/map.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/adc.h> +#include <plat/ata.h> +#include <plat/ehci.h> +#include <plat/fb.h> +#include <plat/fb-s3c2410.h> +#include <plat/hwmon.h> +#include <plat/iic.h> +#include <plat/keypad.h> +#include <plat/mci.h> +#include <plat/nand.h> +#include <plat/sdhci.h> +#include <plat/ts.h> +#include <plat/udc.h> +#include <plat/usb-control.h> +#include <plat/usb-phy.h> +#include <plat/regs-iic.h> +#include <plat/regs-serial.h> +#include <plat/regs-spi.h> + +static u64 samsung_device_dma_mask = DMA_BIT_MASK(32); + +/* AC97 */ +#ifdef CONFIG_CPU_S3C2440 +static struct resource s3c_ac97_resource[] = { + [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97), + [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97), + [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"), + [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"), + [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"), +}; + +struct platform_device s3c_device_ac97 = { + .name = "samsung-ac97", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_ac97_resource), + .resource = s3c_ac97_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; +#endif /* CONFIG_CPU_S3C2440 */ + +/* ADC */ + +#ifdef CONFIG_PLAT_S3C24XX +static struct resource s3c_adc_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC), + [1] = DEFINE_RES_IRQ(IRQ_TC), + [2] = DEFINE_RES_IRQ(IRQ_ADC), +}; + +struct platform_device s3c_device_adc = { + .name = "s3c24xx-adc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_adc_resource), + .resource = s3c_adc_resource, +}; +#endif /* CONFIG_PLAT_S3C24XX */ + +#if defined(CONFIG_SAMSUNG_DEV_ADC) +static struct resource s3c_adc_resource[] = { + [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_TC), + [2] = DEFINE_RES_IRQ(IRQ_ADC), +}; + +struct platform_device s3c_device_adc = { + .name = "samsung-adc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_adc_resource), + .resource = s3c_adc_resource, +}; +#endif /* CONFIG_SAMSUNG_DEV_ADC */ + +/* Camif Controller */ + +#ifdef CONFIG_CPU_S3C2440 +static struct resource s3c_camif_resource[] = { + [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF), + [1] = DEFINE_RES_IRQ(IRQ_CAM), +}; + +struct platform_device s3c_device_camif = { + .name = "s3c2440-camif", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_camif_resource), + .resource = s3c_camif_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; +#endif /* CONFIG_CPU_S3C2440 */ + +/* ASOC DMA */ + +struct platform_device samsung_asoc_dma = { + .name = "samsung-audio", + .id = -1, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; + +struct platform_device samsung_asoc_idma = { + .name = "samsung-idma", + .id = -1, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; + +/* FB */ + +#ifdef CONFIG_S3C_DEV_FB +static struct resource s3c_fb_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K), + [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC), + [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO), + [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM), +}; + +struct platform_device s3c_device_fb = { + .name = "s3c-fb", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_fb_resource), + .resource = s3c_fb_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd) +{ + s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata), + &s3c_device_fb); +} +#endif /* CONFIG_S3C_DEV_FB */ + +/* FIMC */ + +#ifdef CONFIG_S5P_DEV_FIMC0 +static struct resource s5p_fimc0_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_FIMC0), +}; + +struct platform_device s5p_device_fimc0 = { + .name = "s5p-fimc", + .id = 0, + .num_resources = ARRAY_SIZE(s5p_fimc0_resource), + .resource = s5p_fimc0_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device s5p_device_fimc_md = { + .name = "s5p-fimc-md", + .id = -1, +}; +#endif /* CONFIG_S5P_DEV_FIMC0 */ + +#ifdef CONFIG_S5P_DEV_FIMC1 +static struct resource s5p_fimc1_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_FIMC1), +}; + +struct platform_device s5p_device_fimc1 = { + .name = "s5p-fimc", + .id = 1, + .num_resources = ARRAY_SIZE(s5p_fimc1_resource), + .resource = s5p_fimc1_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; +#endif /* CONFIG_S5P_DEV_FIMC1 */ + +#ifdef CONFIG_S5P_DEV_FIMC2 +static struct resource s5p_fimc2_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_FIMC2), +}; + +struct platform_device s5p_device_fimc2 = { + .name = "s5p-fimc", + .id = 2, + .num_resources = ARRAY_SIZE(s5p_fimc2_resource), + .resource = s5p_fimc2_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; +#endif /* CONFIG_S5P_DEV_FIMC2 */ + +#ifdef CONFIG_S5P_DEV_FIMC3 +static struct resource s5p_fimc3_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_FIMC3), +}; + +struct platform_device s5p_device_fimc3 = { + .name = "s5p-fimc", + .id = 3, + .num_resources = ARRAY_SIZE(s5p_fimc3_resource), + .resource = s5p_fimc3_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; +#endif /* CONFIG_S5P_DEV_FIMC3 */ + +/* FIMD0 */ + +#ifdef CONFIG_S5P_DEV_FIMD0 +static struct resource s5p_fimd0_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K), + [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC), + [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO), + [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM), +}; + +struct platform_device s5p_device_fimd0 = { + .name = "s5p-fb", + .id = 0, + .num_resources = ARRAY_SIZE(s5p_fimd0_resource), + .resource = s5p_fimd0_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd) +{ + s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata), + &s5p_device_fimd0); +} +#endif /* CONFIG_S5P_DEV_FIMD0 */ + +/* HWMON */ + +#ifdef CONFIG_S3C_DEV_HWMON +struct platform_device s3c_device_hwmon = { + .name = "s3c-hwmon", + .id = -1, + .dev.parent = &s3c_device_adc.dev, +}; + +void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd) +{ + s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata), + &s3c_device_hwmon); +} +#endif /* CONFIG_S3C_DEV_HWMON */ + +/* HSMMC */ + +#ifdef CONFIG_S3C_DEV_HSMMC +static struct resource s3c_hsmmc_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_HSMMC0), +}; + +struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = { + .max_width = 4, + .host_caps = (MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), + .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, +}; + +struct platform_device s3c_device_hsmmc0 = { + .name = "s3c-sdhci", + .id = 0, + .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), + .resource = s3c_hsmmc_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s3c_hsmmc0_def_platdata, + }, +}; + +void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) +{ + s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata); +} +#endif /* CONFIG_S3C_DEV_HSMMC */ + +#ifdef CONFIG_S3C_DEV_HSMMC1 +static struct resource s3c_hsmmc1_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_HSMMC1), +}; + +struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = { + .max_width = 4, + .host_caps = (MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), + .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, +}; + +struct platform_device s3c_device_hsmmc1 = { + .name = "s3c-sdhci", + .id = 1, + .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource), + .resource = s3c_hsmmc1_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s3c_hsmmc1_def_platdata, + }, +}; + +void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) +{ + s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata); +} +#endif /* CONFIG_S3C_DEV_HSMMC1 */ + +/* HSMMC2 */ + +#ifdef CONFIG_S3C_DEV_HSMMC2 +static struct resource s3c_hsmmc2_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_HSMMC2), +}; + +struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = { + .max_width = 4, + .host_caps = (MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), + .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, +}; + +struct platform_device s3c_device_hsmmc2 = { + .name = "s3c-sdhci", + .id = 2, + .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource), + .resource = s3c_hsmmc2_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s3c_hsmmc2_def_platdata, + }, +}; + +void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) +{ + s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata); +} +#endif /* CONFIG_S3C_DEV_HSMMC2 */ + +#ifdef CONFIG_S3C_DEV_HSMMC3 +static struct resource s3c_hsmmc3_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_HSMMC3), +}; + +struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = { + .max_width = 4, + .host_caps = (MMC_CAP_4_BIT_DATA | + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), + .clk_type = S3C_SDHCI_CLK_DIV_INTERNAL, +}; + +struct platform_device s3c_device_hsmmc3 = { + .name = "s3c-sdhci", + .id = 3, + .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource), + .resource = s3c_hsmmc3_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s3c_hsmmc3_def_platdata, + }, +}; + +void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd) +{ + s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata); +} +#endif /* CONFIG_S3C_DEV_HSMMC3 */ + +/* I2C */ + +static struct resource s3c_i2c0_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_IIC), +}; + +struct platform_device s3c_device_i2c0 = { + .name = "s3c2410-i2c", +#ifdef CONFIG_S3C_DEV_I2C1 + .id = 0, +#else + .id = -1, +#endif + .num_resources = ARRAY_SIZE(s3c_i2c0_resource), + .resource = s3c_i2c0_resource, +}; + +struct s3c2410_platform_i2c default_i2c_data __initdata = { + .flags = 0, + .slave_addr = 0x10, + .frequency = 100*1000, + .sda_delay = 100, +}; + +void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) + pd = &default_i2c_data; + + npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), + &s3c_device_i2c0); + + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c0_cfg_gpio; +} + +#ifdef CONFIG_S3C_DEV_I2C1 +static struct resource s3c_i2c1_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_IIC1), +}; + +struct platform_device s3c_device_i2c1 = { + .name = "s3c2410-i2c", + .id = 1, + .num_resources = ARRAY_SIZE(s3c_i2c1_resource), + .resource = s3c_i2c1_resource, +}; + +void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) { + pd = &default_i2c_data; + pd->bus_num = 1; + } + + npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), + &s3c_device_i2c1); + + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c1_cfg_gpio; +} +#endif /* CONFIG_S3C_DEV_I2C1 */ + +#ifdef CONFIG_S3C_DEV_I2C2 +static struct resource s3c_i2c2_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_IIC2), +}; + +struct platform_device s3c_device_i2c2 = { + .name = "s3c2410-i2c", + .id = 2, + .num_resources = ARRAY_SIZE(s3c_i2c2_resource), + .resource = s3c_i2c2_resource, +}; + +void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) { + pd = &default_i2c_data; + pd->bus_num = 2; + } + + npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), + &s3c_device_i2c2); + + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c2_cfg_gpio; +} +#endif /* CONFIG_S3C_DEV_I2C2 */ + +#ifdef CONFIG_S3C_DEV_I2C3 +static struct resource s3c_i2c3_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_IIC3), +}; + +struct platform_device s3c_device_i2c3 = { + .name = "s3c2440-i2c", + .id = 3, + .num_resources = ARRAY_SIZE(s3c_i2c3_resource), + .resource = s3c_i2c3_resource, +}; + +void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) { + pd = &default_i2c_data; + pd->bus_num = 3; + } + + npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), + &s3c_device_i2c3); + + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c3_cfg_gpio; +} +#endif /*CONFIG_S3C_DEV_I2C3 */ + +#ifdef CONFIG_S3C_DEV_I2C4 +static struct resource s3c_i2c4_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_IIC4), +}; + +struct platform_device s3c_device_i2c4 = { + .name = "s3c2440-i2c", + .id = 4, + .num_resources = ARRAY_SIZE(s3c_i2c4_resource), + .resource = s3c_i2c4_resource, +}; + +void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) { + pd = &default_i2c_data; + pd->bus_num = 4; + } + + npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), + &s3c_device_i2c4); + + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c4_cfg_gpio; +} +#endif /*CONFIG_S3C_DEV_I2C4 */ + +#ifdef CONFIG_S3C_DEV_I2C5 +static struct resource s3c_i2c5_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_IIC5), +}; + +struct platform_device s3c_device_i2c5 = { + .name = "s3c2440-i2c", + .id = 5, + .num_resources = ARRAY_SIZE(s3c_i2c5_resource), + .resource = s3c_i2c5_resource, +}; + +void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) { + pd = &default_i2c_data; + pd->bus_num = 5; + } + + npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), + &s3c_device_i2c5); + + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c5_cfg_gpio; +} +#endif /*CONFIG_S3C_DEV_I2C5 */ + +#ifdef CONFIG_S3C_DEV_I2C6 +static struct resource s3c_i2c6_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_IIC6), +}; + +struct platform_device s3c_device_i2c6 = { + .name = "s3c2440-i2c", + .id = 6, + .num_resources = ARRAY_SIZE(s3c_i2c6_resource), + .resource = s3c_i2c6_resource, +}; + +void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) { + pd = &default_i2c_data; + pd->bus_num = 6; + } + + npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), + &s3c_device_i2c6); + + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c6_cfg_gpio; +} +#endif /* CONFIG_S3C_DEV_I2C6 */ + +#ifdef CONFIG_S3C_DEV_I2C7 +static struct resource s3c_i2c7_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_IIC7), +}; + +struct platform_device s3c_device_i2c7 = { + .name = "s3c2440-i2c", + .id = 7, + .num_resources = ARRAY_SIZE(s3c_i2c7_resource), + .resource = s3c_i2c7_resource, +}; + +void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) { + pd = &default_i2c_data; + pd->bus_num = 7; + } + + npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), + &s3c_device_i2c7); + + if (!npd->cfg_gpio) + npd->cfg_gpio = s3c_i2c7_cfg_gpio; +} +#endif /* CONFIG_S3C_DEV_I2C7 */ + +/* I2C HDMIPHY */ + +#ifdef CONFIG_S5P_DEV_I2C_HDMIPHY +static struct resource s5p_i2c_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY), +}; + +struct platform_device s5p_device_i2c_hdmiphy = { + .name = "s3c2440-hdmiphy-i2c", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_i2c_resource), + .resource = s5p_i2c_resource, +}; + +void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd) +{ + struct s3c2410_platform_i2c *npd; + + if (!pd) { + pd = &default_i2c_data; + + if (soc_is_exynos4210()) + pd->bus_num = 8; + else if (soc_is_s5pv210()) + pd->bus_num = 3; + else + pd->bus_num = 0; + } + + npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c), + &s5p_device_i2c_hdmiphy); +} +#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */ + +/* I2S */ + +#ifdef CONFIG_PLAT_S3C24XX +static struct resource s3c_iis_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS), +}; + +struct platform_device s3c_device_iis = { + .name = "s3c24xx-iis", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_iis_resource), + .resource = s3c_iis_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; +#endif /* CONFIG_PLAT_S3C24XX */ + +#ifdef CONFIG_CPU_S3C2440 +struct platform_device s3c2412_device_iis = { + .name = "s3c2412-iis", + .id = -1, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; +#endif /* CONFIG_CPU_S3C2440 */ + +/* IDE CFCON */ + +#ifdef CONFIG_SAMSUNG_DEV_IDE +static struct resource s3c_cfcon_resource[] = { + [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K), + [1] = DEFINE_RES_IRQ(IRQ_CFCON), +}; + +struct platform_device s3c_device_cfcon = { + .id = 0, + .num_resources = ARRAY_SIZE(s3c_cfcon_resource), + .resource = s3c_cfcon_resource, +}; + +void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata) +{ + s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata), + &s3c_device_cfcon); +} +#endif /* CONFIG_SAMSUNG_DEV_IDE */ + +/* KEYPAD */ + +#ifdef CONFIG_SAMSUNG_DEV_KEYPAD +static struct resource samsung_keypad_resources[] = { + [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32), + [1] = DEFINE_RES_IRQ(IRQ_KEYPAD), +}; + +struct platform_device samsung_device_keypad = { + .name = "samsung-keypad", + .id = -1, + .num_resources = ARRAY_SIZE(samsung_keypad_resources), + .resource = samsung_keypad_resources, +}; + +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd) +{ + struct samsung_keypad_platdata *npd; + + npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata), + &samsung_device_keypad); + + if (!npd->cfg_gpio) + npd->cfg_gpio = samsung_keypad_cfg_gpio; +} +#endif /* CONFIG_SAMSUNG_DEV_KEYPAD */ + +/* LCD Controller */ + +#ifdef CONFIG_PLAT_S3C24XX +static struct resource s3c_lcd_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD), + [1] = DEFINE_RES_IRQ(IRQ_LCD), +}; + +struct platform_device s3c_device_lcd = { + .name = "s3c2410-lcd", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_lcd_resource), + .resource = s3c_lcd_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; + +void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) +{ + struct s3c2410fb_mach_info *npd; + + npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd); + if (npd) { + npd->displays = kmemdup(pd->displays, + sizeof(struct s3c2410fb_display) * npd->num_displays, + GFP_KERNEL); + if (!npd->displays) + printk(KERN_ERR "no memory for LCD display data\n"); + } else { + printk(KERN_ERR "no memory for LCD platform data\n"); + } +} +#endif /* CONFIG_PLAT_S3C24XX */ + +/* MFC */ + +#ifdef CONFIG_S5P_DEV_MFC +static struct resource s5p_mfc_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K), + [1] = DEFINE_RES_IRQ(IRQ_MFC), +}; + +struct platform_device s5p_device_mfc = { + .name = "s5p-mfc", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_mfc_resource), + .resource = s5p_mfc_resource, +}; + +/* + * MFC hardware has 2 memory interfaces which are modelled as two separate + * platform devices to let dma-mapping distinguish between them. + * + * MFC parent device (s5p_device_mfc) must be registered before memory + * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r). + */ + +struct platform_device s5p_device_mfc_l = { + .name = "s5p-mfc-l", + .id = -1, + .dev = { + .parent = &s5p_device_mfc.dev, + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device s5p_device_mfc_r = { + .name = "s5p-mfc-r", + .id = -1, + .dev = { + .parent = &s5p_device_mfc.dev, + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; +#endif /* CONFIG_S5P_DEV_MFC */ + +/* MIPI CSIS */ + +#ifdef CONFIG_S5P_DEV_CSIS0 +static struct resource s5p_mipi_csis0_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0), +}; + +struct platform_device s5p_device_mipi_csis0 = { + .name = "s5p-mipi-csis", + .id = 0, + .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource), + .resource = s5p_mipi_csis0_resource, +}; +#endif /* CONFIG_S5P_DEV_CSIS0 */ + +#ifdef CONFIG_S5P_DEV_CSIS1 +static struct resource s5p_mipi_csis1_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_4K), + [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1), +}; + +struct platform_device s5p_device_mipi_csis1 = { + .name = "s5p-mipi-csis", + .id = 1, + .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource), + .resource = s5p_mipi_csis1_resource, +}; +#endif + +/* NAND */ + +#ifdef CONFIG_S3C_DEV_NAND +static struct resource s3c_nand_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M), +}; + +struct platform_device s3c_device_nand = { + .name = "s3c2410-nand", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_nand_resource), + .resource = s3c_nand_resource, +}; + +/* + * s3c_nand_copy_set() - copy nand set data + * @set: The new structure, directly copied from the old. + * + * Copy all the fields from the NAND set field from what is probably __initdata + * to new kernel memory. The code returns 0 if the copy happened correctly or + * an error code for the calling function to display. + * + * Note, we currently do not try and look to see if we've already copied the + * data in a previous set. + */ +static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set) +{ + void *ptr; + int size; + + size = sizeof(struct mtd_partition) * set->nr_partitions; + if (size) { + ptr = kmemdup(set->partitions, size, GFP_KERNEL); + set->partitions = ptr; + + if (!ptr) + return -ENOMEM; + } + + if (set->nr_map && set->nr_chips) { + size = sizeof(int) * set->nr_chips; + ptr = kmemdup(set->nr_map, size, GFP_KERNEL); + set->nr_map = ptr; + + if (!ptr) + return -ENOMEM; + } + + if (set->ecc_layout) { + ptr = kmemdup(set->ecc_layout, + sizeof(struct nand_ecclayout), GFP_KERNEL); + set->ecc_layout = ptr; + + if (!ptr) + return -ENOMEM; + } + + return 0; +} + +void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand) +{ + struct s3c2410_platform_nand *npd; + int size; + int ret; + + /* note, if we get a failure in allocation, we simply drop out of the + * function. If there is so little memory available at initialisation + * time then there is little chance the system is going to run. + */ + + npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand), + &s3c_device_nand); + if (!npd) + return; + + /* now see if we need to copy any of the nand set data */ + + size = sizeof(struct s3c2410_nand_set) * npd->nr_sets; + if (size) { + struct s3c2410_nand_set *from = npd->sets; + struct s3c2410_nand_set *to; + int i; + + to = kmemdup(from, size, GFP_KERNEL); + npd->sets = to; /* set, even if we failed */ + + if (!to) { + printk(KERN_ERR "%s: no memory for sets\n", __func__); + return; + } + + for (i = 0; i < npd->nr_sets; i++) { + ret = s3c_nand_copy_set(to); + if (ret) { + printk(KERN_ERR "%s: failed to copy set %d\n", + __func__, i); + return; + } + to++; + } + } +} +#endif /* CONFIG_S3C_DEV_NAND */ + +/* ONENAND */ + +#ifdef CONFIG_S3C_DEV_ONENAND +static struct resource s3c_onenand_resources[] = { + [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K), + [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF), + [2] = DEFINE_RES_IRQ(IRQ_ONENAND), +}; + +struct platform_device s3c_device_onenand = { + .name = "samsung-onenand", + .id = 0, + .num_resources = ARRAY_SIZE(s3c_onenand_resources), + .resource = s3c_onenand_resources, +}; +#endif /* CONFIG_S3C_DEV_ONENAND */ + +#ifdef CONFIG_S3C64XX_DEV_ONENAND1 +static struct resource s3c64xx_onenand1_resources[] = { + [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K), + [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF), + [2] = DEFINE_RES_IRQ(IRQ_ONENAND1), +}; + +struct platform_device s3c64xx_device_onenand1 = { + .name = "samsung-onenand", + .id = 1, + .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources), + .resource = s3c64xx_onenand1_resources, +}; + +void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata) +{ + s3c_set_platdata(pdata, sizeof(struct onenand_platform_data), + &s3c64xx_device_onenand1); +} +#endif /* CONFIG_S3C64XX_DEV_ONENAND1 */ + +#ifdef CONFIG_S5P_DEV_ONENAND +static struct resource s5p_onenand_resources[] = { + [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K), + [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K), + [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI), +}; + +struct platform_device s5p_device_onenand = { + .name = "s5pc110-onenand", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_onenand_resources), + .resource = s5p_onenand_resources, +}; +#endif /* CONFIG_S5P_DEV_ONENAND */ + +/* PMU */ + +#ifdef CONFIG_PLAT_S5P +static struct resource s5p_pmu_resource[] = { + DEFINE_RES_IRQ(IRQ_PMU) +}; + +struct platform_device s5p_device_pmu = { + .name = "arm-pmu", + .id = ARM_PMU_DEVICE_CPU, + .num_resources = ARRAY_SIZE(s5p_pmu_resource), + .resource = s5p_pmu_resource, +}; + +static int __init s5p_pmu_init(void) +{ + platform_device_register(&s5p_device_pmu); + return 0; +} +arch_initcall(s5p_pmu_init); +#endif /* CONFIG_PLAT_S5P */ + +/* PWM Timer */ + +#ifdef CONFIG_SAMSUNG_DEV_PWM + +#define TIMER_RESOURCE_SIZE (1) + +#define TIMER_RESOURCE(_tmr, _irq) \ + (struct resource [TIMER_RESOURCE_SIZE]) { \ + [0] = { \ + .start = _irq, \ + .end = _irq, \ + .flags = IORESOURCE_IRQ \ + } \ + } + +#define DEFINE_S3C_TIMER(_tmr_no, _irq) \ + .name = "s3c24xx-pwm", \ + .id = _tmr_no, \ + .num_resources = TIMER_RESOURCE_SIZE, \ + .resource = TIMER_RESOURCE(_tmr_no, _irq), \ + +/* + * since we already have an static mapping for the timer, + * we do not bother setting any IO resource for the base. + */ + +struct platform_device s3c_device_timer[] = { + [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) }, + [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) }, + [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) }, + [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) }, + [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) }, +}; +#endif /* CONFIG_SAMSUNG_DEV_PWM */ + +/* RTC */ + +#ifdef CONFIG_PLAT_S3C24XX +static struct resource s3c_rtc_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_RTC), + [2] = DEFINE_RES_IRQ(IRQ_TICK), +}; + +struct platform_device s3c_device_rtc = { + .name = "s3c2410-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_rtc_resource), + .resource = s3c_rtc_resource, +}; +#endif /* CONFIG_PLAT_S3C24XX */ + +#ifdef CONFIG_S3C_DEV_RTC +static struct resource s3c_rtc_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM), + [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC), +}; + +struct platform_device s3c_device_rtc = { + .name = "s3c64xx-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_rtc_resource), + .resource = s3c_rtc_resource, +}; +#endif /* CONFIG_S3C_DEV_RTC */ + +/* SDI */ + +#ifdef CONFIG_PLAT_S3C24XX +static struct resource s3c_sdi_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI), + [1] = DEFINE_RES_IRQ(IRQ_SDI), +}; + +struct platform_device s3c_device_sdi = { + .name = "s3c2410-sdi", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_sdi_resource), + .resource = s3c_sdi_resource, +}; + +void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) +{ + s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata), + &s3c_device_sdi); +} +#endif /* CONFIG_PLAT_S3C24XX */ + +/* SPI */ + +#ifdef CONFIG_PLAT_S3C24XX +static struct resource s3c_spi0_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32), + [1] = DEFINE_RES_IRQ(IRQ_SPI0), +}; + +struct platform_device s3c_device_spi0 = { + .name = "s3c2410-spi", + .id = 0, + .num_resources = ARRAY_SIZE(s3c_spi0_resource), + .resource = s3c_spi0_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; + +static struct resource s3c_spi1_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32), + [1] = DEFINE_RES_IRQ(IRQ_SPI1), +}; + +struct platform_device s3c_device_spi1 = { + .name = "s3c2410-spi", + .id = 1, + .num_resources = ARRAY_SIZE(s3c_spi1_resource), + .resource = s3c_spi1_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; +#endif /* CONFIG_PLAT_S3C24XX */ + +/* Touchscreen */ + +#ifdef CONFIG_PLAT_S3C24XX +static struct resource s3c_ts_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC), + [1] = DEFINE_RES_IRQ(IRQ_TC), +}; + +struct platform_device s3c_device_ts = { + .name = "s3c2410-ts", + .id = -1, + .dev.parent = &s3c_device_adc.dev, + .num_resources = ARRAY_SIZE(s3c_ts_resource), + .resource = s3c_ts_resource, +}; + +void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info) +{ + s3c_set_platdata(hard_s3c2410ts_info, + sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts); +} +#endif /* CONFIG_PLAT_S3C24XX */ + +#ifdef CONFIG_SAMSUNG_DEV_TS +static struct resource s3c_ts_resource[] = { + [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_TC), +}; + +static struct s3c2410_ts_mach_info default_ts_data __initdata = { + .delay = 10000, + .presc = 49, + .oversampling_shift = 2, +}; + +struct platform_device s3c_device_ts = { + .name = "s3c64xx-ts", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_ts_resource), + .resource = s3c_ts_resource, +}; + +void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd) +{ + if (!pd) + pd = &default_ts_data; + + s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info), + &s3c_device_ts); +} +#endif /* CONFIG_SAMSUNG_DEV_TS */ + +/* TV */ + +#ifdef CONFIG_S5P_DEV_TV + +static struct resource s5p_hdmi_resources[] = { + [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M), + [1] = DEFINE_RES_IRQ(IRQ_HDMI), +}; + +struct platform_device s5p_device_hdmi = { + .name = "s5p-hdmi", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_hdmi_resources), + .resource = s5p_hdmi_resources, +}; + +static struct resource s5p_sdo_resources[] = { + [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K), + [1] = DEFINE_RES_IRQ(IRQ_SDO), +}; + +struct platform_device s5p_device_sdo = { + .name = "s5p-sdo", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_sdo_resources), + .resource = s5p_sdo_resources, +}; + +static struct resource s5p_mixer_resources[] = { + [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"), + [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"), + [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"), +}; + +struct platform_device s5p_device_mixer = { + .name = "s5p-mixer", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_mixer_resources), + .resource = s5p_mixer_resources, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; +#endif /* CONFIG_S5P_DEV_TV */ + +/* USB */ + +#ifdef CONFIG_S3C_DEV_USB_HOST +static struct resource s3c_usb_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_USBH), +}; + +struct platform_device s3c_device_ohci = { + .name = "s3c2410-ohci", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usb_resource), + .resource = s3c_usb_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; + +/* + * s3c_ohci_set_platdata - initialise OHCI device platform data + * @info: The platform data. + * + * This call copies the @info passed in and sets the device .platform_data + * field to that copy. The @info is copied so that the original can be marked + * __initdata. + */ + +void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info) +{ + s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info), + &s3c_device_ohci); +} +#endif /* CONFIG_S3C_DEV_USB_HOST */ + +/* USB Device (Gadget) */ + +#ifdef CONFIG_PLAT_S3C24XX +static struct resource s3c_usbgadget_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV), + [1] = DEFINE_RES_IRQ(IRQ_USBD), +}; + +struct platform_device s3c_device_usbgadget = { + .name = "s3c2410-usbgadget", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usbgadget_resource), + .resource = s3c_usbgadget_resource, +}; + +void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd) +{ + s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget); +} +#endif /* CONFIG_PLAT_S3C24XX */ + +/* USB EHCI Host Controller */ + +#ifdef CONFIG_S5P_DEV_USB_EHCI +static struct resource s5p_ehci_resource[] = { + [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256), + [1] = DEFINE_RES_IRQ(IRQ_USB_HOST), +}; + +struct platform_device s5p_device_ehci = { + .name = "s5p-ehci", + .id = -1, + .num_resources = ARRAY_SIZE(s5p_ehci_resource), + .resource = s5p_ehci_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + } +}; + +void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd) +{ + struct s5p_ehci_platdata *npd; + + npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata), + &s5p_device_ehci); + + if (!npd->phy_init) + npd->phy_init = s5p_usb_phy_init; + if (!npd->phy_exit) + npd->phy_exit = s5p_usb_phy_exit; +} +#endif /* CONFIG_S5P_DEV_USB_EHCI */ + +/* USB HSOTG */ + +#ifdef CONFIG_S3C_DEV_USB_HSOTG +static struct resource s3c_usb_hsotg_resources[] = { + [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_16K), + [1] = DEFINE_RES_IRQ(IRQ_OTG), +}; + +struct platform_device s3c_device_usb_hsotg = { + .name = "s3c-hsotg", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources), + .resource = s3c_usb_hsotg_resources, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; +#endif /* CONFIG_S3C_DEV_USB_HSOTG */ + +/* USB High Spped 2.0 Device (Gadget) */ + +#ifdef CONFIG_PLAT_S3C24XX +static struct resource s3c_hsudc_resource[] = { + [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC), + [1] = DEFINE_RES_IRQ(IRQ_USBD), +}; + +struct platform_device s3c_device_usb_hsudc = { + .name = "s3c-hsudc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_hsudc_resource), + .resource = s3c_hsudc_resource, + .dev = { + .dma_mask = &samsung_device_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd) +{ + s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc); +} +#endif /* CONFIG_PLAT_S3C24XX */ + +/* WDT */ + +#ifdef CONFIG_S3C_DEV_WDT +static struct resource s3c_wdt_resource[] = { + [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K), + [1] = DEFINE_RES_IRQ(IRQ_WDT), +}; + +struct platform_device s3c_device_wdt = { + .name = "s3c2410-wdt", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_wdt_resource), + .resource = s3c_wdt_resource, +}; +#endif /* CONFIG_S3C_DEV_WDT */ diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c deleted file mode 100644 index 1c0b0401594b..000000000000 --- a/arch/arm/plat-samsung/gpio-config.c +++ /dev/null @@ -1,431 +0,0 @@ -/* linux/arch/arm/plat-s3c/gpio-config.c - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008-2010 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series GPIO configuration core - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/gpio.h> -#include <linux/io.h> - -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> - -int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - unsigned long flags; - int offset; - int ret; - - if (!chip) - return -EINVAL; - - offset = pin - chip->chip.base; - - s3c_gpio_lock(chip, flags); - ret = s3c_gpio_do_setcfg(chip, offset, config); - s3c_gpio_unlock(chip, flags); - - return ret; -} -EXPORT_SYMBOL(s3c_gpio_cfgpin); - -int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, - unsigned int cfg) -{ - int ret; - - for (; nr > 0; nr--, start++) { - ret = s3c_gpio_cfgpin(start, cfg); - if (ret != 0) - return ret; - } - - return 0; -} -EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range); - -int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, - unsigned int cfg, s3c_gpio_pull_t pull) -{ - int ret; - - for (; nr > 0; nr--, start++) { - s3c_gpio_setpull(start, pull); - ret = s3c_gpio_cfgpin(start, cfg); - if (ret != 0) - return ret; - } - - return 0; -} -EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range); - -unsigned s3c_gpio_getcfg(unsigned int pin) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - unsigned long flags; - unsigned ret = 0; - int offset; - - if (chip) { - offset = pin - chip->chip.base; - - s3c_gpio_lock(chip, flags); - ret = s3c_gpio_do_getcfg(chip, offset); - s3c_gpio_unlock(chip, flags); - } - - return ret; -} -EXPORT_SYMBOL(s3c_gpio_getcfg); - - -int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - unsigned long flags; - int offset, ret; - - if (!chip) - return -EINVAL; - - offset = pin - chip->chip.base; - - s3c_gpio_lock(chip, flags); - ret = s3c_gpio_do_setpull(chip, offset, pull); - s3c_gpio_unlock(chip, flags); - - return ret; -} -EXPORT_SYMBOL(s3c_gpio_setpull); - -s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - unsigned long flags; - int offset; - u32 pup = 0; - - if (chip) { - offset = pin - chip->chip.base; - - s3c_gpio_lock(chip, flags); - pup = s3c_gpio_do_getpull(chip, offset); - s3c_gpio_unlock(chip, flags); - } - - return (__force s3c_gpio_pull_t)pup; -} -EXPORT_SYMBOL(s3c_gpio_getpull); - -#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX -int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg) -{ - void __iomem *reg = chip->base; - unsigned int shift = off; - u32 con; - - if (s3c_gpio_is_cfg_special(cfg)) { - cfg &= 0xf; - - /* Map output to 0, and SFN2 to 1 */ - cfg -= 1; - if (cfg > 1) - return -EINVAL; - - cfg <<= shift; - } - - con = __raw_readl(reg); - con &= ~(0x1 << shift); - con |= cfg; - __raw_writel(con, reg); - - return 0; -} - -unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip, - unsigned int off) -{ - u32 con; - - con = __raw_readl(chip->base); - con >>= off; - con &= 1; - con++; - - return S3C_GPIO_SFN(con); -} - -int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg) -{ - void __iomem *reg = chip->base; - unsigned int shift = off * 2; - u32 con; - - if (s3c_gpio_is_cfg_special(cfg)) { - cfg &= 0xf; - if (cfg > 3) - return -EINVAL; - - cfg <<= shift; - } - - con = __raw_readl(reg); - con &= ~(0x3 << shift); - con |= cfg; - __raw_writel(con, reg); - - return 0; -} - -unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip, - unsigned int off) -{ - u32 con; - - con = __raw_readl(chip->base); - con >>= off * 2; - con &= 3; - - /* this conversion works for IN and OUT as well as special mode */ - return S3C_GPIO_SPECIAL(con); -} -#endif - -#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX -int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg) -{ - void __iomem *reg = chip->base; - unsigned int shift = (off & 7) * 4; - u32 con; - - if (off < 8 && chip->chip.ngpio > 8) - reg -= 4; - - if (s3c_gpio_is_cfg_special(cfg)) { - cfg &= 0xf; - cfg <<= shift; - } - - con = __raw_readl(reg); - con &= ~(0xf << shift); - con |= cfg; - __raw_writel(con, reg); - - return 0; -} - -unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, - unsigned int off) -{ - void __iomem *reg = chip->base; - unsigned int shift = (off & 7) * 4; - u32 con; - - if (off < 8 && chip->chip.ngpio > 8) - reg -= 4; - - con = __raw_readl(reg); - con >>= shift; - con &= 0xf; - - /* this conversion works for IN and OUT as well as special mode */ - return S3C_GPIO_SPECIAL(con); -} - -#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */ - -#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN -int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull) -{ - void __iomem *reg = chip->base + 0x08; - int shift = off * 2; - u32 pup; - - pup = __raw_readl(reg); - pup &= ~(3 << shift); - pup |= pull << shift; - __raw_writel(pup, reg); - - return 0; -} - -s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, - unsigned int off) -{ - void __iomem *reg = chip->base + 0x08; - int shift = off * 2; - u32 pup = __raw_readl(reg); - - pup >>= shift; - pup &= 0x3; - return (__force s3c_gpio_pull_t)pup; -} - -#ifdef CONFIG_S3C_GPIO_PULL_S3C2443 -int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull) -{ - switch (pull) { - case S3C_GPIO_PULL_NONE: - pull = 0x01; - break; - case S3C_GPIO_PULL_UP: - pull = 0x00; - break; - case S3C_GPIO_PULL_DOWN: - pull = 0x02; - break; - } - return s3c_gpio_setpull_updown(chip, off, pull); -} - -s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip, - unsigned int off) -{ - s3c_gpio_pull_t pull; - - pull = s3c_gpio_getpull_updown(chip, off); - - switch (pull) { - case 0x00: - pull = S3C_GPIO_PULL_UP; - break; - case 0x01: - case 0x03: - pull = S3C_GPIO_PULL_NONE; - break; - case 0x02: - pull = S3C_GPIO_PULL_DOWN; - break; - } - - return pull; -} -#endif -#endif - -#if defined(CONFIG_S3C_GPIO_PULL_UP) || defined(CONFIG_S3C_GPIO_PULL_DOWN) -static int s3c_gpio_setpull_1(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull, - s3c_gpio_pull_t updown) -{ - void __iomem *reg = chip->base + 0x08; - u32 pup = __raw_readl(reg); - - if (pull == updown) - pup &= ~(1 << off); - else if (pull == S3C_GPIO_PULL_NONE) - pup |= (1 << off); - else - return -EINVAL; - - __raw_writel(pup, reg); - return 0; -} - -static s3c_gpio_pull_t s3c_gpio_getpull_1(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t updown) -{ - void __iomem *reg = chip->base + 0x08; - u32 pup = __raw_readl(reg); - - pup &= (1 << off); - return pup ? S3C_GPIO_PULL_NONE : updown; -} -#endif /* CONFIG_S3C_GPIO_PULL_UP || CONFIG_S3C_GPIO_PULL_DOWN */ - -#ifdef CONFIG_S3C_GPIO_PULL_UP -s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip, - unsigned int off) -{ - return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP); -} - -int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull) -{ - return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP); -} -#endif /* CONFIG_S3C_GPIO_PULL_UP */ - -#ifdef CONFIG_S3C_GPIO_PULL_DOWN -s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip, - unsigned int off) -{ - return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN); -} - -int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull) -{ - return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN); -} -#endif /* CONFIG_S3C_GPIO_PULL_DOWN */ - -#ifdef CONFIG_S5P_GPIO_DRVSTR -s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - unsigned int off; - void __iomem *reg; - int shift; - u32 drvstr; - - if (!chip) - return -EINVAL; - - off = pin - chip->chip.base; - shift = off * 2; - reg = chip->base + 0x0C; - - drvstr = __raw_readl(reg); - drvstr = drvstr >> shift; - drvstr &= 0x3; - - return (__force s5p_gpio_drvstr_t)drvstr; -} -EXPORT_SYMBOL(s5p_gpio_get_drvstr); - -int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr) -{ - struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); - unsigned int off; - void __iomem *reg; - int shift; - u32 tmp; - - if (!chip) - return -EINVAL; - - off = pin - chip->chip.base; - shift = off * 2; - reg = chip->base + 0x0C; - - tmp = __raw_readl(reg); - tmp &= ~(0x3 << shift); - tmp |= drvstr << shift; - - __raw_writel(tmp, reg); - - return 0; -} -EXPORT_SYMBOL(s5p_gpio_set_drvstr); -#endif /* CONFIG_S5P_GPIO_DRVSTR */ diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c deleted file mode 100644 index 7743c4b8b2fb..000000000000 --- a/arch/arm/plat-samsung/gpio.c +++ /dev/null @@ -1,167 +0,0 @@ -/* linux/arch/arm/plat-s3c/gpio.c - * - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C series GPIO core - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/spinlock.h> - -#include <plat/gpio-core.h> - -#ifdef CONFIG_S3C_GPIO_TRACK -struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; - -static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip) -{ - unsigned int gpn; - int i; - - gpn = chip->chip.base; - for (i = 0; i < chip->chip.ngpio; i++, gpn++) { - BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios)); - s3c_gpios[gpn] = chip; - } -} -#endif /* CONFIG_S3C_GPIO_TRACK */ - -/* Default routines for controlling GPIO, based on the original S3C24XX - * GPIO functions which deal with the case where each gpio bank of the - * chip is as following: - * - * base + 0x00: Control register, 2 bits per gpio - * gpio n: 2 bits starting at (2*n) - * 00 = input, 01 = output, others mean special-function - * base + 0x04: Data register, 1 bit per gpio - * bit n: data bit n -*/ - -static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long flags; - unsigned long con; - - s3c_gpio_lock(ourchip, flags); - - con = __raw_readl(base + 0x00); - con &= ~(3 << (offset * 2)); - - __raw_writel(con, base + 0x00); - - s3c_gpio_unlock(ourchip, flags); - return 0; -} - -static int s3c_gpiolib_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long flags; - unsigned long dat; - unsigned long con; - - s3c_gpio_lock(ourchip, flags); - - dat = __raw_readl(base + 0x04); - dat &= ~(1 << offset); - if (value) - dat |= 1 << offset; - __raw_writel(dat, base + 0x04); - - con = __raw_readl(base + 0x00); - con &= ~(3 << (offset * 2)); - con |= 1 << (offset * 2); - - __raw_writel(con, base + 0x00); - __raw_writel(dat, base + 0x04); - - s3c_gpio_unlock(ourchip, flags); - return 0; -} - -static void s3c_gpiolib_set(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long flags; - unsigned long dat; - - s3c_gpio_lock(ourchip, flags); - - dat = __raw_readl(base + 0x04); - dat &= ~(1 << offset); - if (value) - dat |= 1 << offset; - __raw_writel(dat, base + 0x04); - - s3c_gpio_unlock(ourchip, flags); -} - -static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - unsigned long val; - - val = __raw_readl(ourchip->base + 0x04); - val >>= offset; - val &= 1; - - return val; -} - -__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip) -{ - struct gpio_chip *gc = &chip->chip; - int ret; - - BUG_ON(!chip->base); - BUG_ON(!gc->label); - BUG_ON(!gc->ngpio); - - spin_lock_init(&chip->lock); - - if (!gc->direction_input) - gc->direction_input = s3c_gpiolib_input; - if (!gc->direction_output) - gc->direction_output = s3c_gpiolib_output; - if (!gc->set) - gc->set = s3c_gpiolib_set; - if (!gc->get) - gc->get = s3c_gpiolib_get; - -#ifdef CONFIG_PM - if (chip->pm != NULL) { - if (!chip->pm->save || !chip->pm->resume) - printk(KERN_ERR "gpio: %s has missing PM functions\n", - gc->label); - } else - printk(KERN_ERR "gpio: %s has no PM function\n", gc->label); -#endif - - /* gpiochip_add() prints own failure message on error. */ - ret = gpiochip_add(gc); - if (ret >= 0) - s3c_gpiolib_track(chip); -} - -int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) -{ - struct s3c_gpio_chip *s3c_chip = container_of(chip, - struct s3c_gpio_chip, chip); - - return s3c_chip->irq_base + offset; -} diff --git a/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h b/arch/arm/plat-samsung/include/plat/audio-simtec.h index de5e88fdcb31..5345364e7420 100644 --- a/arch/arm/plat-s3c24xx/include/plat/audio-simtec.h +++ b/arch/arm/plat-samsung/include/plat/audio-simtec.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c24xx/include/plat/audio-simtec.h +/* arch/arm/plat-samsung/include/plat/audio-simtec.h * * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ diff --git a/arch/arm/plat-s5p/include/plat/camport.h b/arch/arm/plat-samsung/include/plat/camport.h index 71688c8ba288..a5708bf84b3a 100644 --- a/arch/arm/plat-s5p/include/plat/camport.h +++ b/arch/arm/plat-samsung/include/plat/camport.h @@ -8,8 +8,8 @@ * published by the Free Software Foundation. */ -#ifndef PLAT_S5P_CAMPORT_H_ -#define PLAT_S5P_CAMPORT_H_ __FILE__ +#ifndef __PLAT_SAMSUNG_CAMPORT_H_ +#define __PLAT_SAMSUNG_CAMPORT_H_ __FILE__ enum s5p_camport_id { S5P_CAMPORT_A, @@ -25,4 +25,4 @@ enum s5p_camport_id { int s5pv210_fimc_setup_gpio(enum s5p_camport_id id); int exynos4_fimc_setup_gpio(enum s5p_camport_id id); -#endif +#endif /* __PLAT_SAMSUNG_CAMPORT_H */ diff --git a/arch/arm/plat-s3c24xx/include/plat/common-smdk.h b/arch/arm/plat-samsung/include/plat/common-smdk.h index 58d9094c935c..ba028f1ed30b 100644 --- a/arch/arm/plat-s3c24xx/include/plat/common-smdk.h +++ b/arch/arm/plat-samsung/include/plat/common-smdk.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/common-smdk.h +/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h * * Copyright (c) 2006 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h index d623235ae961..dac4760c0f0a 100644 --- a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h +++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s3c/include/plat/cpu-freq.h +/* arch/arm/plat-samsung/include/plat/cpu-freq-core.h * * Copyright (c) 2006-2009 Simtec Electronics * http://armlinux.simtec.co.uk/ @@ -195,7 +195,8 @@ struct s3c_cpufreq_info { extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info); -extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no); +extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, + unsigned int plls_no); /* exports and utilities for debugfs */ extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 24ebb1e1de41..ab633c9c2aec 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -30,30 +30,24 @@ extern struct s3c24xx_uart_resources s5p_uart_resources[]; extern struct platform_device *s3c24xx_uart_devs[]; extern struct platform_device *s3c24xx_uart_src[]; -extern struct platform_device s3c_device_timer[]; - +extern struct platform_device s3c64xx_device_ac97; extern struct platform_device s3c64xx_device_iis0; extern struct platform_device s3c64xx_device_iis1; extern struct platform_device s3c64xx_device_iisv4; - -extern struct platform_device s3c64xx_device_spi0; -extern struct platform_device s3c64xx_device_spi1; - -extern struct platform_device samsung_asoc_dma; -extern struct platform_device samsung_asoc_idma; - +extern struct platform_device s3c64xx_device_onenand1; extern struct platform_device s3c64xx_device_pcm0; extern struct platform_device s3c64xx_device_pcm1; +extern struct platform_device s3c64xx_device_spi0; +extern struct platform_device s3c64xx_device_spi1; -extern struct platform_device s3c64xx_device_ac97; - -extern struct platform_device s3c_device_ts; - +extern struct platform_device s3c_device_adc; +extern struct platform_device s3c_device_cfcon; extern struct platform_device s3c_device_fb; -extern struct platform_device s5p_device_fimd0; -extern struct platform_device s3c_device_ohci; -extern struct platform_device s3c_device_lcd; -extern struct platform_device s3c_device_wdt; +extern struct platform_device s3c_device_hwmon; +extern struct platform_device s3c_device_hsmmc0; +extern struct platform_device s3c_device_hsmmc1; +extern struct platform_device s3c_device_hsmmc2; +extern struct platform_device s3c_device_hsmmc3; extern struct platform_device s3c_device_i2c0; extern struct platform_device s3c_device_i2c1; extern struct platform_device s3c_device_i2c2; @@ -62,93 +56,90 @@ extern struct platform_device s3c_device_i2c4; extern struct platform_device s3c_device_i2c5; extern struct platform_device s3c_device_i2c6; extern struct platform_device s3c_device_i2c7; +extern struct platform_device s3c_device_iis; +extern struct platform_device s3c_device_lcd; +extern struct platform_device s3c_device_nand; +extern struct platform_device s3c_device_ohci; +extern struct platform_device s3c_device_onenand; extern struct platform_device s3c_device_rtc; -extern struct platform_device s3c_device_adc; extern struct platform_device s3c_device_sdi; -extern struct platform_device s3c_device_iis; -extern struct platform_device s3c_device_hwmon; -extern struct platform_device s3c_device_hsmmc0; -extern struct platform_device s3c_device_hsmmc1; -extern struct platform_device s3c_device_hsmmc2; -extern struct platform_device s3c_device_hsmmc3; -extern struct platform_device s3c_device_cfcon; - extern struct platform_device s3c_device_spi0; extern struct platform_device s3c_device_spi1; - -extern struct platform_device s5pc100_device_spi0; -extern struct platform_device s5pc100_device_spi1; -extern struct platform_device s5pc100_device_spi2; -extern struct platform_device s5pv210_device_spi0; -extern struct platform_device s5pv210_device_spi1; -extern struct platform_device s5p64x0_device_spi0; -extern struct platform_device s5p64x0_device_spi1; - -extern struct platform_device s3c_device_hwmon; - -extern struct platform_device s3c_device_nand; -extern struct platform_device s3c_device_onenand; -extern struct platform_device s3c64xx_device_onenand1; -extern struct platform_device s5p_device_onenand; - +extern struct platform_device s3c_device_ts; +extern struct platform_device s3c_device_timer[]; extern struct platform_device s3c_device_usbgadget; -extern struct platform_device s3c_device_usb_hsudc; extern struct platform_device s3c_device_usb_hsotg; +extern struct platform_device s3c_device_usb_hsudc; +extern struct platform_device s3c_device_wdt; -extern struct platform_device s5pv210_device_ac97; -extern struct platform_device s5pv210_device_pcm0; -extern struct platform_device s5pv210_device_pcm1; -extern struct platform_device s5pv210_device_pcm2; -extern struct platform_device s5pv210_device_iis0; -extern struct platform_device s5pv210_device_iis1; -extern struct platform_device s5pv210_device_iis2; -extern struct platform_device s5pv210_device_spdif; - -extern struct platform_device exynos4_device_ac97; -extern struct platform_device exynos4_device_pcm0; -extern struct platform_device exynos4_device_pcm1; -extern struct platform_device exynos4_device_pcm2; -extern struct platform_device exynos4_device_i2s0; -extern struct platform_device exynos4_device_i2s1; -extern struct platform_device exynos4_device_i2s2; -extern struct platform_device exynos4_device_spdif; -extern struct platform_device exynos4_device_pd[]; -extern struct platform_device exynos4_device_ahci; -extern struct platform_device exynos4_device_dwmci; +extern struct platform_device s5p_device_ehci; +extern struct platform_device s5p_device_fimc0; +extern struct platform_device s5p_device_fimc1; +extern struct platform_device s5p_device_fimc2; +extern struct platform_device s5p_device_fimc3; +extern struct platform_device s5p_device_fimc_md; +extern struct platform_device s5p_device_fimd0; +extern struct platform_device s5p_device_hdmi; +extern struct platform_device s5p_device_i2c_hdmiphy; +extern struct platform_device s5p_device_mfc; +extern struct platform_device s5p_device_mfc_l; +extern struct platform_device s5p_device_mfc_r; +extern struct platform_device s5p_device_mipi_csis0; +extern struct platform_device s5p_device_mipi_csis1; +extern struct platform_device s5p_device_mixer; +extern struct platform_device s5p_device_onenand; +extern struct platform_device s5p_device_sdo; -extern struct platform_device s5p6440_device_pcm; extern struct platform_device s5p6440_device_iis; +extern struct platform_device s5p6440_device_pcm; extern struct platform_device s5p6450_device_iis0; extern struct platform_device s5p6450_device_iis1; extern struct platform_device s5p6450_device_iis2; extern struct platform_device s5p6450_device_pcm0; +extern struct platform_device s5p64x0_device_spi0; +extern struct platform_device s5p64x0_device_spi1; + extern struct platform_device s5pc100_device_ac97; -extern struct platform_device s5pc100_device_pcm0; -extern struct platform_device s5pc100_device_pcm1; extern struct platform_device s5pc100_device_iis0; extern struct platform_device s5pc100_device_iis1; extern struct platform_device s5pc100_device_iis2; +extern struct platform_device s5pc100_device_pcm0; +extern struct platform_device s5pc100_device_pcm1; extern struct platform_device s5pc100_device_spdif; +extern struct platform_device s5pc100_device_spi0; +extern struct platform_device s5pc100_device_spi1; +extern struct platform_device s5pc100_device_spi2; -extern struct platform_device samsung_device_keypad; - -extern struct platform_device s5p_device_fimc0; -extern struct platform_device s5p_device_fimc1; -extern struct platform_device s5p_device_fimc2; -extern struct platform_device s5p_device_fimc3; - -extern struct platform_device s5p_device_mfc; -extern struct platform_device s5p_device_mfc_l; -extern struct platform_device s5p_device_mfc_r; -extern struct platform_device s5p_device_mipi_csis0; -extern struct platform_device s5p_device_mipi_csis1; - -extern struct platform_device s5p_device_ehci; +extern struct platform_device s5pv210_device_ac97; +extern struct platform_device s5pv210_device_iis0; +extern struct platform_device s5pv210_device_iis1; +extern struct platform_device s5pv210_device_iis2; +extern struct platform_device s5pv210_device_pcm0; +extern struct platform_device s5pv210_device_pcm1; +extern struct platform_device s5pv210_device_pcm2; +extern struct platform_device s5pv210_device_spdif; +extern struct platform_device s5pv210_device_spi0; +extern struct platform_device s5pv210_device_spi1; +extern struct platform_device exynos4_device_ac97; +extern struct platform_device exynos4_device_ahci; +extern struct platform_device exynos4_device_dwmci; +extern struct platform_device exynos4_device_i2s0; +extern struct platform_device exynos4_device_i2s1; +extern struct platform_device exynos4_device_i2s2; +extern struct platform_device exynos4_device_pcm0; +extern struct platform_device exynos4_device_pcm1; +extern struct platform_device exynos4_device_pcm2; +extern struct platform_device exynos4_device_pd[]; +extern struct platform_device exynos4_device_spdif; extern struct platform_device exynos4_device_sysmmu; +extern struct platform_device samsung_asoc_dma; +extern struct platform_device samsung_asoc_idma; +extern struct platform_device samsung_device_keypad; + /* s3c2440 specific devices */ #ifdef CONFIG_CPU_S3C2440 diff --git a/arch/arm/plat-s5p/include/plat/ehci.h b/arch/arm/plat-samsung/include/plat/ehci.h index 6ae6810c7569..5f28cae18582 100644 --- a/arch/arm/plat-s5p/include/plat/ehci.h +++ b/arch/arm/plat-samsung/include/plat/ehci.h @@ -8,8 +8,8 @@ * option) any later version. */ -#ifndef __PLAT_S5P_EHCI_H -#define __PLAT_S5P_EHCI_H +#ifndef __PLAT_SAMSUNG_EHCI_H +#define __PLAT_SAMSUNG_EHCI_H __FILE__ struct s5p_ehci_platdata { int (*phy_init)(struct platform_device *pdev, int type); @@ -18,4 +18,4 @@ struct s5p_ehci_platdata { extern void s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd); -#endif /* __PLAT_S5P_EHCI_H */ +#endif /* __PLAT_SAMSUNG_EHCI_H */ diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-samsung/include/plat/exynos4.h index f680a143e38c..20d73bf77537 100644 --- a/arch/arm/plat-s5p/include/plat/exynos4.h +++ b/arch/arm/plat-samsung/include/plat/exynos4.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/include/plat/exynos4.h +/* linux/arch/arm/plat-samsung/include/plat/exynos4.h * * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com diff --git a/arch/arm/plat-samsung/include/plat/fb-s3c2410.h b/arch/arm/plat-samsung/include/plat/fb-s3c2410.h new file mode 100644 index 000000000000..4e5d9588b5ba --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/fb-s3c2410.h @@ -0,0 +1,72 @@ +/* arch/arm/plat-samsung/include/plat/fb-s3c2410.h + * + * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org> + * + * Inspired by pxafb.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_FB_S3C2410_H +#define __ASM_PLAT_FB_S3C2410_H __FILE__ + +struct s3c2410fb_hw { + unsigned long lcdcon1; + unsigned long lcdcon2; + unsigned long lcdcon3; + unsigned long lcdcon4; + unsigned long lcdcon5; +}; + +/* LCD description */ +struct s3c2410fb_display { + /* LCD type */ + unsigned type; + + /* Screen size */ + unsigned short width; + unsigned short height; + + /* Screen info */ + unsigned short xres; + unsigned short yres; + unsigned short bpp; + + unsigned pixclock; /* pixclock in picoseconds */ + unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */ + unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */ + unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */ + unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */ + unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */ + unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */ + + /* lcd configuration registers */ + unsigned long lcdcon5; +}; + +struct s3c2410fb_mach_info { + + struct s3c2410fb_display *displays; /* attached diplays info */ + unsigned num_displays; /* number of defined displays */ + unsigned default_display; + + /* GPIOs */ + + unsigned long gpcup; + unsigned long gpcup_mask; + unsigned long gpccon; + unsigned long gpccon_mask; + unsigned long gpdup; + unsigned long gpdup_mask; + unsigned long gpdcon; + unsigned long gpdcon_mask; + + /* lpc3600 control register */ + unsigned long lpcsel; +}; + +extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *); + +#endif /* __ASM_PLAT_FB_S3C2410_H */ diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index 01f10e4d00c7..0fedf47fa502 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h @@ -109,4 +109,11 @@ extern void s5pv210_fb_gpio_setup_24bpp(void); */ extern void exynos4_fimd0_gpio_setup_24bpp(void); +/** + * s5p64x0_fb_gpio_setup_24bpp() - S5P6440/S5P6450 setup function for 24bpp LCD + * + * Initialise the GPIO for an 24bpp LCD display on the RGB interface. + */ +extern void s5p64x0_fb_gpio_setup_24bpp(void); + #endif /* __PLAT_S3C_FB_H */ diff --git a/arch/arm/plat-s3c24xx/include/plat/fiq.h b/arch/arm/plat-samsung/include/plat/fiq.h index 8521b8372c5f..535d06a35628 100644 --- a/arch/arm/plat-s3c24xx/include/plat/fiq.h +++ b/arch/arm/plat-samsung/include/plat/fiq.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/fiq.h +/* linux/arch/arm/plat-samsung/include/plat/fiq.h * * Copyright (c) 2009 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index 9a4e53d52967..a181d7ce81cf 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h @@ -1,11 +1,11 @@ -/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h +/* linux/arch/arm/plat-samsung/include/plat/gpio-cfg-helper.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <ben@simtec.co.uk> * - * S3C Platform - GPIO pin configuration helper definitions + * Samsung Platform - GPIO pin configuration helper definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -24,120 +24,30 @@ * by disabling interrupts. */ -static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int config) +static inline int samsung_gpio_do_setcfg(struct samsung_gpio_chip *chip, + unsigned int off, unsigned int config) { return (chip->config->set_config)(chip, off, config); } -static inline unsigned s3c_gpio_do_getcfg(struct s3c_gpio_chip *chip, - unsigned int off) +static inline unsigned samsung_gpio_do_getcfg(struct samsung_gpio_chip *chip, + unsigned int off) { return (chip->config->get_config)(chip, off); } -static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull) +static inline int samsung_gpio_do_setpull(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull) { return (chip->config->set_pull)(chip, off, pull); } -static inline s3c_gpio_pull_t s3c_gpio_do_getpull(struct s3c_gpio_chip *chip, - unsigned int off) +static inline samsung_gpio_pull_t samsung_gpio_do_getpull(struct samsung_gpio_chip *chip, + unsigned int off) { return chip->config->get_pull(chip, off); } -/** - * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration. - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @cfg: The configuration value to set. - * - * This helper deal with the GPIO cases where the control register - * has two bits of configuration per gpio, which have the following - * functions: - * 00 = input - * 01 = output - * 1x = special function -*/ -extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg); - -/** - * s3c_gpio_getcfg_s3c24xx - S3C24XX style GPIO configuration read. - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * - * The reverse of s3c_gpio_setcfg_s3c24xx(). Will return a value whicg - * could be directly passed back to s3c_gpio_setcfg_s3c24xx(), from the - * S3C_GPIO_SPECIAL() macro. - */ -unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip, - unsigned int off); - -/** - * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A) - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @cfg: The configuration value to set. - * - * This helper deal with the GPIO cases where the control register - * has one bit of configuration for the gpio, where setting the bit - * means the pin is in special function mode and unset means output. -*/ -extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg); - - -/** - * s3c_gpio_getcfg_s3c24xx_a - S3C24XX style GPIO configuration read (Bank A) - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * - * The reverse of s3c_gpio_setcfg_s3c24xx_a() turning an GPIO into a usable - * GPIO configuration value. - * - * @sa s3c_gpio_getcfg_s3c24xx - * @sa s3c_gpio_getcfg_s3c64xx_4bit - */ -extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip, - unsigned int off); - -/** - * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config. - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * @cfg: The configuration value to set. - * - * This helper deal with the GPIO cases where the control register has 4 bits - * of control per GPIO, generally in the form of: - * 0000 = Input - * 0001 = Output - * others = Special functions (dependent on bank) - * - * Note, since the code to deal with the case where there are two control - * registers instead of one, we do not have a separate set of functions for - * each case. -*/ -extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, - unsigned int off, unsigned int cfg); - - -/** - * s3c_gpio_getcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config read. - * @chip: The gpio chip that is being configured. - * @off: The offset for the GPIO being configured. - * - * The reverse of s3c_gpio_setcfg_s3c64xx_4bit(), turning a gpio configuration - * register setting into a value the software can use, such as could be passed - * to s3c_gpio_setcfg_s3c64xx_4bit(). - * - * @sa s3c_gpio_getcfg_s3c24xx - */ -extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, - unsigned int off); - /* Pull-{up,down} resistor controls. * * S3C2410,S3C2440 = Pull-UP, @@ -147,7 +57,7 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, */ /** - * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none. + * s3c24xx_gpio_setpull_1up() - Pull configuration for choice of up or none. * @chip: The gpio chip that is being configured. * @off: The offset for the GPIO being configured. * @param: pull: The pull mode being requested. @@ -155,11 +65,11 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, * This is a helper function for the case where we have GPIOs with one * bit configuring the presence of a pull-up resistor. */ -extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull); +extern int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull); /** - * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none + * s3c24xx_gpio_setpull_1down() - Pull configuration for choice of down or none * @chip: The gpio chip that is being configured * @off: The offset for the GPIO being configured * @param: pull: The pull mode being requested @@ -167,11 +77,13 @@ extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, * This is a helper function for the case where we have GPIOs with one * bit configuring the presence of a pull-down resistor. */ -extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull); +extern int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull); /** - * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none + * samsung_gpio_setpull_upown() - Pull configuration for choice of up, + * down or none + * * @chip: The gpio chip that is being configured. * @off: The offset for the GPIO being configured. * @param: pull: The pull mode being requested. @@ -183,45 +95,46 @@ extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, * 01 = Pull-up resistor connected * 10 = Pull-down resistor connected */ -extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull); - +extern int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull); /** - * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none + * samsung_gpio_getpull_updown() - Get configuration for choice of up, + * down or none + * * @chip: The gpio chip that the GPIO pin belongs to * @off: The offset to the pin to get the configuration of. * - * This helper function reads the state of the pull-{up,down} resistor for the - * given GPIO in the same case as s3c_gpio_setpull_upown. + * This helper function reads the state of the pull-{up,down} resistor + * for the given GPIO in the same case as samsung_gpio_setpull_upown. */ -extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, - unsigned int off); +extern samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip, + unsigned int off); /** - * s3c_gpio_getpull_1up() - Get configuration for choice of up or none + * s3c24xx_gpio_getpull_1up() - Get configuration for choice of up or none * @chip: The gpio chip that the GPIO pin belongs to * @off: The offset to the pin to get the configuration of. * * This helper function reads the state of the pull-up resistor for the - * given GPIO in the same case as s3c_gpio_setpull_1up. + * given GPIO in the same case as s3c24xx_gpio_setpull_1up. */ -extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip, - unsigned int off); +extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip, + unsigned int off); /** - * s3c_gpio_getpull_1down() - Get configuration for choice of down or none + * s3c24xx_gpio_getpull_1down() - Get configuration for choice of down or none * @chip: The gpio chip that the GPIO pin belongs to * @off: The offset to the pin to get the configuration of. * * This helper function reads the state of the pull-down resistor for the - * given GPIO in the same case as s3c_gpio_setpull_1down. + * given GPIO in the same case as s3c24xx_gpio_setpull_1down. */ -extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip, - unsigned int off); +extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip, + unsigned int off); /** - * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. + * s3c2443_gpio_setpull() - Pull configuration for s3c2443. * @chip: The gpio chip that is being configured. * @off: The offset for the GPIO being configured. * @param: pull: The pull mode being requested. @@ -233,19 +146,18 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip, * 10 = Pull-down resistor connected * x1 = No pull up resistor */ -extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull); +extern int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull); /** - * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors + * s3c2443_gpio_getpull() - Get configuration for s3c2443 pull resistors * @chip: The gpio chip that the GPIO pin belongs to. * @off: The offset to the pin to get the configuration of. * * This helper function reads the state of the pull-{up,down} resistor for the - * given GPIO in the same case as s3c_gpio_setpull_upown. + * given GPIO in the same case as samsung_gpio_setpull_upown. */ -extern s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip, +extern samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip, unsigned int off); #endif /* __PLAT_GPIO_CFG_HELPERS_H */ - diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index 1762dcb4cb9e..d48245bb02b3 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h @@ -24,14 +24,14 @@ #ifndef __PLAT_GPIO_CFG_H #define __PLAT_GPIO_CFG_H __FILE__ -typedef unsigned int __bitwise__ s3c_gpio_pull_t; +typedef unsigned int __bitwise__ samsung_gpio_pull_t; typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; /* forward declaration if gpio-core.h hasn't been included */ -struct s3c_gpio_chip; +struct samsung_gpio_chip; /** - * struct s3c_gpio_cfg GPIO configuration + * struct samsung_gpio_cfg GPIO configuration * @cfg_eint: Configuration setting when used for external interrupt source * @get_pull: Read the current pull configuration for the GPIO * @set_pull: Set the current pull configuraiton for the GPIO @@ -44,20 +44,20 @@ struct s3c_gpio_chip; * per-bank configuration information that other systems such as the * external interrupt code will need. * - * @sa s3c_gpio_cfgpin + * @sa samsung_gpio_cfgpin * @sa s3c_gpio_getcfg * @sa s3c_gpio_setpull * @sa s3c_gpio_getpull */ -struct s3c_gpio_cfg { +struct samsung_gpio_cfg { unsigned int cfg_eint; - s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs); - int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs, - s3c_gpio_pull_t pull); + samsung_gpio_pull_t (*get_pull)(struct samsung_gpio_chip *chip, unsigned offs); + int (*set_pull)(struct samsung_gpio_chip *chip, unsigned offs, + samsung_gpio_pull_t pull); - unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs); - int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs, + unsigned (*get_config)(struct samsung_gpio_chip *chip, unsigned offs); + int (*set_config)(struct samsung_gpio_chip *chip, unsigned offs, unsigned config); }; @@ -69,7 +69,7 @@ struct s3c_gpio_cfg { #define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) #define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) -#define s3c_gpio_is_cfg_special(_cfg) \ +#define samsung_gpio_is_cfg_special(_cfg) \ (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) /** @@ -128,9 +128,9 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, * up or down settings, and it may be dependent on the chip that is being * used to whether the particular mode is available. */ -#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) -#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01) -#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02) +#define S3C_GPIO_PULL_NONE ((__force samsung_gpio_pull_t)0x00) +#define S3C_GPIO_PULL_DOWN ((__force samsung_gpio_pull_t)0x01) +#define S3C_GPIO_PULL_UP ((__force samsung_gpio_pull_t)0x02) /** * s3c_gpio_setpull() - set the state of a gpio pin pull resistor @@ -143,7 +143,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, * * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. */ -extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); +extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull); /** * s3c_gpio_getpull() - get the pull resistor state of a gpio pin @@ -151,7 +151,7 @@ extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); * * Read the pull resistor value for the specified pin. */ -extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); +extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin); /* configure `all` aspects of an gpio */ @@ -170,7 +170,7 @@ extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); * @sa s3c_gpio_cfgpin_range */ extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, - unsigned int cfg, s3c_gpio_pull_t pull); + unsigned int cfg, samsung_gpio_pull_t pull); static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size, unsigned int cfg) diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 8cad4cf19c3c..1fe6917f6a2a 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -25,22 +25,22 @@ * specific code. */ -struct s3c_gpio_chip; +struct samsung_gpio_chip; /** - * struct s3c_gpio_pm - power management (suspend/resume) information + * struct samsung_gpio_pm - power management (suspend/resume) information * @save: Routine to save the state of the GPIO block * @resume: Routine to resume the GPIO block. */ -struct s3c_gpio_pm { - void (*save)(struct s3c_gpio_chip *chip); - void (*resume)(struct s3c_gpio_chip *chip); +struct samsung_gpio_pm { + void (*save)(struct samsung_gpio_chip *chip); + void (*resume)(struct samsung_gpio_chip *chip); }; -struct s3c_gpio_cfg; +struct samsung_gpio_cfg; /** - * struct s3c_gpio_chip - wrapper for specific implementation of gpio + * struct samsung_gpio_chip - wrapper for specific implementation of gpio * @chip: The chip structure to be exported via gpiolib. * @base: The base pointer to the gpio configuration registers. * @group: The group register number for gpio interrupt support. @@ -60,10 +60,10 @@ struct s3c_gpio_cfg; * CPU cores trying to get one lock for different GPIO banks, where each * bank of GPIO has its own register space and configuration registers. */ -struct s3c_gpio_chip { +struct samsung_gpio_chip { struct gpio_chip chip; - struct s3c_gpio_cfg *config; - struct s3c_gpio_pm *pm; + struct samsung_gpio_cfg *config; + struct samsung_gpio_pm *pm; void __iomem *base; int irq_base; int group; @@ -73,58 +73,11 @@ struct s3c_gpio_chip { #endif }; -static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) +static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc) { - return container_of(gpc, struct s3c_gpio_chip, chip); + return container_of(gpc, struct samsung_gpio_chip, chip); } -/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip. - * @chip: The chip to register - * - * This is a wrapper to gpiochip_add() that takes our specific gpio chip - * information and makes the necessary alterations for the platform and - * notes the information for use with the configuration systems and any - * other parts of the system. - */ -extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); - -/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios - * for use with the configuration calls, and other parts of the s3c gpiolib - * support code. - * - * Not all s3c support code will need this, as some configurations of cpu - * may only support one or two different configuration options and have an - * easy gpio to s3c_gpio_chip mapping function. If this is the case, then - * the machine support file should provide its own s3c_gpiolib_getchip() - * and any other necessary functions. - */ - -/** - * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config. - * @chip: The gpio chip that is being configured. - * @nr_chips: The no of chips (gpio ports) for the GPIO being configured. - * - * This helper deal with the GPIO cases where the control register has 4 bits - * of control per GPIO, generally in the form of: - * 0000 = Input - * 0001 = Output - * others = Special functions (dependent on bank) - * - * Note, since the code to deal with the case where there are two control - * registers instead of one, we do not have a separate set of function - * (samsung_gpiolib_add_4bit2_chips)for each case. - */ -extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, - int nr_chips); -extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, - int nr_chips); -extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, - int nr_chips); - -extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); -extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); - - /** * samsung_gpiolib_to_irq - convert gpio pin to irq number * @chip: The gpio chip that the pin belongs to. @@ -136,36 +89,36 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset); /* exported for core SoC support to change */ -extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default; +extern struct samsung_gpio_cfg s3c24xx_gpiocfg_default; #ifdef CONFIG_S3C_GPIO_TRACK -extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; +extern struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END]; -static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) +static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chip) { return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; } #else -/* machine specific code should provide s3c_gpiolib_getchip */ +/* machine specific code should provide samsung_gpiolib_getchip */ #include <mach/gpio-track.h> -static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } +static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { } #endif #ifdef CONFIG_PM -extern struct s3c_gpio_pm s3c_gpio_pm_1bit; -extern struct s3c_gpio_pm s3c_gpio_pm_2bit; -extern struct s3c_gpio_pm s3c_gpio_pm_4bit; +extern struct samsung_gpio_pm samsung_gpio_pm_1bit; +extern struct samsung_gpio_pm samsung_gpio_pm_2bit; +extern struct samsung_gpio_pm samsung_gpio_pm_4bit; #define __gpio_pm(x) x #else -#define s3c_gpio_pm_1bit NULL -#define s3c_gpio_pm_2bit NULL -#define s3c_gpio_pm_4bit NULL +#define samsung_gpio_pm_1bit NULL +#define samsung_gpio_pm_2bit NULL +#define samsung_gpio_pm_4bit NULL #define __gpio_pm(x) NULL #endif /* CONFIG_PM */ /* locking wrappers to deal with multiple access to the same gpio bank */ -#define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) -#define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) +#define samsung_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) +#define samsung_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h new file mode 100644 index 000000000000..bab139201761 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/gpio-fns.h @@ -0,0 +1,98 @@ +/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h + * + * Copyright (c) 2003-2009 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C2410 - hardware + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __MACH_GPIO_FNS_H +#define __MACH_GPIO_FNS_H __FILE__ + +/* These functions are in the to-be-removed category and it is strongly + * encouraged not to use these in new code. They will be marked deprecated + * very soon. + * + * Most of the functionality can be either replaced by the gpiocfg calls + * for the s3c platform or by the generic GPIOlib API. + * + * As of 2.6.35-rc, these will be removed, with the few drivers using them + * either replaced or given a wrapper until the calls can be removed. +*/ + +#include <plat/gpio-cfg.h> + +static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg) +{ + /* 1:1 mapping between cfgpin and setcfg calls at the moment */ + s3c_gpio_cfgpin(pin, cfg); +} + +/* external functions for GPIO support + * + * These allow various different clients to access the same GPIO + * registers without conflicting. If your driver only owns the entire + * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. +*/ + +extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); + +/* s3c2410_gpio_getirq + * + * turn the given pin number into the corresponding IRQ number + * + * returns: + * < 0 = no interrupt for this pin + * >=0 = interrupt number for the pin +*/ + +extern int s3c2410_gpio_getirq(unsigned int pin); + +/* s3c2410_gpio_irqfilter + * + * set the irq filtering on the given pin + * + * on = 0 => disable filtering + * 1 => enable filtering + * + * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with + * width of filter (0 through 63) + * + * +*/ + +extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, + unsigned int config); + +/* s3c2410_gpio_pullup + * + * This call should be replaced with s3c_gpio_setpull(). + * + * As a note, there is currently no distinction between pull-up and pull-down + * in the s3c24xx series devices with only an on/off configuration. + */ + +/* s3c2410_gpio_pullup + * + * configure the pull-up control on the given pin + * + * to = 1 => disable the pull-up + * 0 => enable the pull-up + * + * eg; + * + * s3c2410_gpio_pullup(S3C2410_GPB(0), 0); + * s3c2410_gpio_pullup(S3C2410_GPE(8), 0); +*/ + +extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); + +extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); + +extern unsigned int s3c2410_gpio_getpin(unsigned int pin); + +#endif /* __MACH_GPIO_FNS_H */ diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h index 56b0059439e1..51d52e767a19 100644 --- a/arch/arm/plat-samsung/include/plat/iic.h +++ b/arch/arm/plat-samsung/include/plat/iic.h @@ -60,6 +60,7 @@ extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c); extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c); extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c); extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c); +extern void s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *i2c); /* defined by architecture to configure gpio */ extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h index ec087d6054b1..e21a89bc26c9 100644 --- a/arch/arm/plat-s3c24xx/include/plat/irq.h +++ b/arch/arm/plat-samsung/include/plat/irq.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/irq.h +/* linux/arch/arm/plat-samsung/include/plat/irq.h * * Copyright (c) 2004-2005 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> @@ -25,9 +25,9 @@ extern struct irq_chip s3c_irq_level_chip; extern struct irq_chip s3c_irq_chip; -static inline void -s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, - int subcheck) +static inline void s3c_irqsub_mask(unsigned int irqno, + unsigned int parentbit, + int subcheck) { unsigned long mask; unsigned long submask; @@ -39,17 +39,16 @@ s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit, /* check to see if we need to mask the parent IRQ */ - if ((submask & subcheck) == subcheck) { + if ((submask & subcheck) == subcheck) __raw_writel(mask | parentbit, S3C2410_INTMSK); - } /* write back masks */ __raw_writel(submask, S3C2410_INTSUBMSK); } -static inline void -s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit) +static inline void s3c_irqsub_unmask(unsigned int irqno, + unsigned int parentbit) { unsigned long mask; unsigned long submask; @@ -66,8 +65,9 @@ s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit) } -static inline void -s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group) +static inline void s3c_irqsub_maskack(unsigned int irqno, + unsigned int parentmask, + unsigned int group) { unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); @@ -86,8 +86,9 @@ s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int gro } } -static inline void -s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group) +static inline void s3c_irqsub_ack(unsigned int irqno, + unsigned int parentmask, + unsigned int group) { unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0); diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h index 144dbfc6506d..08d1a7ef97b7 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-samsung/include/plat/irqs.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/include/plat/irqs.h +/* linux/arch/arm/plat-samsung/include/plat/irqs.h * * Copyright (c) 2009 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -10,8 +10,8 @@ * published by the Free Software Foundation. */ -#ifndef __ASM_PLAT_S5P_IRQS_H -#define __ASM_PLAT_S5P_IRQS_H __FILE__ +#ifndef __PLAT_SAMSUNG_IRQS_H +#define __PLAT_SAMSUNG_IRQS_H __FILE__ /* we keep the first set of CPU IRQs out of the range of * the ISA space, so that the PC104 has them to itself @@ -77,4 +77,4 @@ #define S5P_IRQ_TYPE_EDGE_RISING (0x03) #define S5P_IRQ_TYPE_EDGE_BOTH (0x04) -#endif /* __ASM_PLAT_S5P_IRQS_H */ +#endif /* __PLAT_SAMSUNG_IRQS_H */ diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-samsung/include/plat/mci.h index 2ac2b21ec490..c42d31711944 100644 --- a/arch/arm/plat-s3c24xx/include/plat/mci.h +++ b/arch/arm/plat-samsung/include/plat/mci.h @@ -27,11 +27,11 @@ * to a non-zero value, otherwise the default of 3.2-3.4V is used. */ struct s3c24xx_mci_pdata { - unsigned int no_wprotect : 1; - unsigned int no_detect : 1; - unsigned int wprotect_invert : 1; - unsigned int detect_invert : 1; /* set => detect active high. */ - unsigned int use_dma : 1; + unsigned int no_wprotect:1; + unsigned int no_detect:1; + unsigned int wprotect_invert:1; + unsigned int detect_invert:1; /* set => detect active high */ + unsigned int use_dma:1; unsigned int gpio_detect; unsigned int gpio_wprotect; diff --git a/arch/arm/plat-s5p/include/plat/mfc.h b/arch/arm/plat-samsung/include/plat/mfc.h index 6697f8cb2949..ac13227272f0 100644 --- a/arch/arm/plat-s5p/include/plat/mfc.h +++ b/arch/arm/plat-samsung/include/plat/mfc.h @@ -7,8 +7,8 @@ * option) any later version. */ -#ifndef __PLAT_S5P_MFC_H -#define __PLAT_S5P_MFC_H +#ifndef __PLAT_SAMSUNG_MFC_H +#define __PLAT_SAMSUNG_MFC_H __FILE__ /** * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver @@ -24,4 +24,4 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, phys_addr_t lbase, unsigned int lsize); -#endif /* __PLAT_S5P_MFC_H */ +#endif /* __PLAT_SAMSUNG_MFC_H */ diff --git a/arch/arm/plat-s5p/include/plat/mipi_csis.h b/arch/arm/plat-samsung/include/plat/mipi_csis.h index 9bd254c5ed22..c45b1e8d4c2e 100644 --- a/arch/arm/plat-s5p/include/plat/mipi_csis.h +++ b/arch/arm/plat-samsung/include/plat/mipi_csis.h @@ -8,8 +8,8 @@ * published by the Free Software Foundation. */ -#ifndef PLAT_S5P_MIPI_CSIS_H_ -#define PLAT_S5P_MIPI_CSIS_H_ __FILE__ +#ifndef __PLAT_SAMSUNG_MIPI_CSIS_H_ +#define __PLAT_SAMSUNG_MIPI_CSIS_H_ __FILE__ struct platform_device; @@ -40,4 +40,4 @@ struct s5p_platform_mipi_csis { */ int s5p_csis_phy_enable(struct platform_device *pdev, bool on); -#endif /* PLAT_S5P_MIPI_CSIS_H_ */ +#endif /* __PLAT_SAMSUNG_MIPI_CSIS_H_ */ diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-samsung/include/plat/pll.h index 3e21b9444cc5..357af7c1c664 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-samsung/include/plat/pll.h @@ -1,11 +1,14 @@ -/* arch/arm/plat-s5p/include/plat/pll.h +/* linux/arch/arm/plat-samsung/include/plat/pll.h * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * - * S5P PLL code + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ * - * Based on arch/arm/plat-s3c64xx/include/plat/pll.h + * Samsung PLL codes * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,6 +17,111 @@ #include <asm/div64.h> +#define S3C24XX_PLL_MDIV_MASK (0xFF) +#define S3C24XX_PLL_PDIV_MASK (0x1F) +#define S3C24XX_PLL_SDIV_MASK (0x3) +#define S3C24XX_PLL_MDIV_SHIFT (12) +#define S3C24XX_PLL_PDIV_SHIFT (4) +#define S3C24XX_PLL_SDIV_SHIFT (0) + +static inline unsigned int s3c24xx_get_pll(unsigned int pllval, + unsigned int baseclk) +{ + unsigned int mdiv, pdiv, sdiv; + uint64_t fvco; + + mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK; + pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK; + sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK; + + fvco = (uint64_t)baseclk * (mdiv + 8); + do_div(fvco, (pdiv + 2) << sdiv); + + return (unsigned int)fvco; +} + +#define S3C2416_PLL_MDIV_MASK (0x3FF) +#define S3C2416_PLL_PDIV_MASK (0x3F) +#define S3C2416_PLL_SDIV_MASK (0x7) +#define S3C2416_PLL_MDIV_SHIFT (14) +#define S3C2416_PLL_PDIV_SHIFT (5) +#define S3C2416_PLL_SDIV_SHIFT (0) + +static inline unsigned int s3c2416_get_pll(unsigned int pllval, + unsigned int baseclk) +{ + unsigned int mdiv, pdiv, sdiv; + uint64_t fvco; + + mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK; + pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK; + sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK; + + fvco = (uint64_t)baseclk * mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned int)fvco; +} + +#define S3C6400_PLL_MDIV_MASK (0x3FF) +#define S3C6400_PLL_PDIV_MASK (0x3F) +#define S3C6400_PLL_SDIV_MASK (0x7) +#define S3C6400_PLL_MDIV_SHIFT (16) +#define S3C6400_PLL_PDIV_SHIFT (8) +#define S3C6400_PLL_SDIV_SHIFT (0) + +static inline unsigned long s3c6400_get_pll(unsigned long baseclk, + u32 pllcon) +{ + u32 mdiv, pdiv, sdiv; + u64 fvco = baseclk; + + mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK; + pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK; + sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +#define PLL6553X_MDIV_MASK (0x7F) +#define PLL6553X_PDIV_MASK (0x1F) +#define PLL6553X_SDIV_MASK (0x3) +#define PLL6553X_KDIV_MASK (0xFFFF) +#define PLL6553X_MDIV_SHIFT (16) +#define PLL6553X_PDIV_SHIFT (8) +#define PLL6553X_SDIV_SHIFT (0) + +static inline unsigned long s3c_get_pll6553x(unsigned long baseclk, + u32 pll_con0, u32 pll_con1) +{ + unsigned long result; + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK; + pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK; + sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK; + kdiv = pll_con1 & PLL6553X_KDIV_MASK; + + /* + * We need to multiple baseclk by mdiv (the integer part) and kdiv + * which is in 2^16ths, so shift mdiv up (does not overflow) and + * add kdiv before multiplying. The use of tmp is to avoid any + * overflows before shifting bac down into result when multipling + * by the mdiv and kdiv pair. + */ + + tmp = baseclk; + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + + return result; +} + #define PLL35XX_MDIV_MASK (0x3FF) #define PLL35XX_PDIV_MASK (0x3F) #define PLL35XX_SDIV_MASK (0x7) @@ -97,15 +205,24 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, return (unsigned long)fvco; } -#define PLL46XX_KDIV_MASK (0xFFFF) -#define PLL4650C_KDIV_MASK (0xFFF) +/* CON0 bit-fields */ #define PLL46XX_MDIV_MASK (0x1FF) #define PLL46XX_PDIV_MASK (0x3F) #define PLL46XX_SDIV_MASK (0x7) +#define PLL46XX_LOCKED_SHIFT (29) #define PLL46XX_MDIV_SHIFT (16) #define PLL46XX_PDIV_SHIFT (8) #define PLL46XX_SDIV_SHIFT (0) +/* CON1 bit-fields */ +#define PLL46XX_MRR_MASK (0x1F) +#define PLL46XX_MFR_MASK (0x3F) +#define PLL46XX_KDIV_MASK (0xFFFF) +#define PLL4650C_KDIV_MASK (0xFFF) +#define PLL46XX_MRR_SHIFT (24) +#define PLL46XX_MFR_SHIFT (16) +#define PLL46XX_KDIV_SHIFT (0) + enum pll46xx_type_t { pll_4600, pll_4650, @@ -123,6 +240,7 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; + kdiv = pll_con1 & PLL46XX_KDIV_MASK; if (pll_type == pll_4650c) kdiv = pll_con1 & PLL4650C_KDIV_MASK; @@ -148,6 +266,7 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, #define PLL90XX_PDIV_MASK (0x3F) #define PLL90XX_SDIV_MASK (0x7) #define PLL90XX_KDIV_MASK (0xffff) +#define PLL90XX_LOCKED_SHIFT (29) #define PLL90XX_MDIV_SHIFT (16) #define PLL90XX_PDIV_SHIFT (8) #define PLL90XX_SDIV_SHIFT (0) @@ -165,7 +284,8 @@ static inline unsigned long s5p_get_pll90xx(unsigned long baseclk, sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK; kdiv = pll_conk & PLL90XX_KDIV_MASK; - /* We need to multiple baseclk by mdiv (the integer part) and kdiv + /* + * We need to multiple baseclk by mdiv (the integer part) and kdiv * which is in 2^16ths, so shift mdiv up (does not overflow) and * add kdiv before multiplying. The use of tmp is to avoid any * overflows before shifting bac down into result when multipling diff --git a/arch/arm/plat-samsung/include/plat/pll6553x.h b/arch/arm/plat-samsung/include/plat/pll6553x.h deleted file mode 100644 index b8b7e1d884f8..000000000000 --- a/arch/arm/plat-samsung/include/plat/pll6553x.h +++ /dev/null @@ -1,51 +0,0 @@ -/* arch/arm/plat-samsung/include/plat/pll6553x.h - * partially from arch/arm/mach-s3c64xx/include/mach/pll.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Samsung PLL6553x PLL code - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/* S3C6400 and compatible (S3C2416, etc.) EPLL code */ - -#define PLL6553X_MDIV_MASK ((1 << (23-16)) - 1) -#define PLL6553X_PDIV_MASK ((1 << (13-8)) - 1) -#define PLL6553X_SDIV_MASK ((1 << (2-0)) - 1) -#define PLL6553X_MDIV_SHIFT (16) -#define PLL6553X_PDIV_SHIFT (8) -#define PLL6553X_SDIV_SHIFT (0) -#define PLL6553X_KDIV_MASK (0xffff) - -static inline unsigned long s3c_get_pll6553x(unsigned long baseclk, - u32 pll0, u32 pll1) -{ - unsigned long result; - u32 mdiv, pdiv, sdiv, kdiv; - u64 tmp; - - mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK; - pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK; - sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK; - kdiv = pll1 & PLL6553X_KDIV_MASK; - - /* We need to multiple baseclk by mdiv (the integer part) and kdiv - * which is in 2^16ths, so shift mdiv up (does not overflow) and - * add kdiv before multiplying. The use of tmp is to avoid any - * overflows before shifting bac down into result when multipling - * by the mdiv and kdiv pair. - */ - - tmp = baseclk; - tmp *= (mdiv << 16) + kdiv; - do_div(tmp, (pdiv << sdiv)); - result = tmp >> 16; - - return result; -} diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index f6749916d194..dcf68709f9cf 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -165,20 +165,20 @@ extern void s3c_pm_check_store(void); extern void s3c_pm_configure_extint(void); /** - * s3c_pm_restore_gpios() - restore the state of the gpios after sleep. + * samsung_pm_restore_gpios() - restore the state of the gpios after sleep. * * Restore the state of the GPIO pins after sleep, which may involve ensuring * that we do not glitch the state of the pins from that the bootloader's * resume code has done. */ -extern void s3c_pm_restore_gpios(void); +extern void samsung_pm_restore_gpios(void); /** - * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. + * samsung_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. * - * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios(). + * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios(). */ -extern void s3c_pm_save_gpios(void); +extern void samsung_pm_save_gpios(void); extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); diff --git a/arch/arm/mach-exynos4/include/mach/pwm-clock.h b/arch/arm/plat-samsung/include/plat/pwm-clock.h index 8e12090287bb..bf6a60eb6237 100644 --- a/arch/arm/mach-exynos4/include/mach/pwm-clock.h +++ b/arch/arm/plat-samsung/include/plat/pwm-clock.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h +/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h * * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com @@ -8,17 +8,15 @@ * Ben Dooks <ben@simtec.co.uk> * http://armlinux.simtec.co.uk/ * - * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h - * - * EXYNOS4 - pwm clock and timer support + * SAMSUNG - pwm clock and timer support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#ifndef __ASM_ARCH_PWMCLK_H -#define __ASM_ARCH_PWMCLK_H __FILE__ +#ifndef __ASM_PLAT_PWM_CLOCK_H +#define __ASM_PLAT_PWM_CLOCK_H __FILE__ /** * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk @@ -29,7 +27,14 @@ */ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) { - return tcfg == S3C64XX_TCFG1_MUX_TCLK; + if (soc_is_s3c24xx()) + return tcfg == S3C2410_TCFG1_MUX_TCLK; + else if (soc_is_s3c64xx() || soc_is_s5pc100()) + return tcfg >= S3C64XX_TCFG1_MUX_TCLK; + else if (soc_is_s5p6440() || soc_is_s5p6450()) + return 0; + else + return tcfg == S3C64XX_TCFG1_MUX_TCLK; } /** @@ -41,7 +46,10 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) */ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) { - return 1 << tcfg1; + if (soc_is_s3c24xx()) + return 1 << (tcfg1 + 1); + else + return 1 << tcfg1; } /** @@ -51,7 +59,10 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) */ static inline unsigned int pwm_tdiv_has_div1(void) { - return 1; + if (soc_is_s3c24xx()) + return 0; + else + return 1; } /** @@ -62,9 +73,9 @@ static inline unsigned int pwm_tdiv_has_div1(void) */ static inline unsigned long pwm_tdiv_div_bits(unsigned int div) { - return ilog2(div); + if (soc_is_s3c24xx()) + return ilog2(div) - 1; + else + return ilog2(div); } - -#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK - -#endif /* __ASM_ARCH_PWMCLK_H */ +#endif /* __ASM_PLAT_PWM_CLOCK_H */ diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-samsung/include/plat/regs-dma.h index 1b0f4c36d384..178bccbe4804 100644 --- a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h +++ b/arch/arm/plat-samsung/include/plat/regs-dma.h @@ -1,4 +1,4 @@ -/* arch/arm/mach-s3c2410/include/mach/dma.h +/* arch/arm/plat-samsung/include/plat/regs-dma.h * * Copyright (C) 2003-2006 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> @@ -10,7 +10,8 @@ * published by the Free Software Foundation. */ -/* DMA Register definitions */ +#ifndef __ASM_PLAT_REGS_DMA_H +#define __ASM_PLAT_REGS_DMA_H __FILE__ #define S3C2410_DMA_DISRC (0x00) #define S3C2410_DMA_DISRCC (0x04) @@ -24,74 +25,75 @@ #define S3C2412_DMA_DMAREQSEL (0x24) #define S3C2443_DMA_DMAREQSEL (0x24) -#define S3C2410_DISRCC_INC (1<<0) -#define S3C2410_DISRCC_APB (1<<1) +#define S3C2410_DISRCC_INC (1 << 0) +#define S3C2410_DISRCC_APB (1 << 1) -#define S3C2410_DMASKTRIG_STOP (1<<2) -#define S3C2410_DMASKTRIG_ON (1<<1) -#define S3C2410_DMASKTRIG_SWTRIG (1<<0) +#define S3C2410_DMASKTRIG_STOP (1 << 2) +#define S3C2410_DMASKTRIG_ON (1 << 1) +#define S3C2410_DMASKTRIG_SWTRIG (1 << 0) -#define S3C2410_DCON_DEMAND (0<<31) -#define S3C2410_DCON_HANDSHAKE (1<<31) -#define S3C2410_DCON_SYNC_PCLK (0<<30) -#define S3C2410_DCON_SYNC_HCLK (1<<30) +#define S3C2410_DCON_DEMAND (0 << 31) +#define S3C2410_DCON_HANDSHAKE (1 << 31) +#define S3C2410_DCON_SYNC_PCLK (0 << 30) +#define S3C2410_DCON_SYNC_HCLK (1 << 30) -#define S3C2410_DCON_INTREQ (1<<29) +#define S3C2410_DCON_INTREQ (1 << 29) -#define S3C2410_DCON_CH0_XDREQ0 (0<<24) -#define S3C2410_DCON_CH0_UART0 (1<<24) -#define S3C2410_DCON_CH0_SDI (2<<24) -#define S3C2410_DCON_CH0_TIMER (3<<24) -#define S3C2410_DCON_CH0_USBEP1 (4<<24) +#define S3C2410_DCON_CH0_XDREQ0 (0 << 24) +#define S3C2410_DCON_CH0_UART0 (1 << 24) +#define S3C2410_DCON_CH0_SDI (2 << 24) +#define S3C2410_DCON_CH0_TIMER (3 << 24) +#define S3C2410_DCON_CH0_USBEP1 (4 << 24) -#define S3C2410_DCON_CH1_XDREQ1 (0<<24) -#define S3C2410_DCON_CH1_UART1 (1<<24) -#define S3C2410_DCON_CH1_I2SSDI (2<<24) -#define S3C2410_DCON_CH1_SPI (3<<24) -#define S3C2410_DCON_CH1_USBEP2 (4<<24) +#define S3C2410_DCON_CH1_XDREQ1 (0 << 24) +#define S3C2410_DCON_CH1_UART1 (1 << 24) +#define S3C2410_DCON_CH1_I2SSDI (2 << 24) +#define S3C2410_DCON_CH1_SPI (3 << 24) +#define S3C2410_DCON_CH1_USBEP2 (4 << 24) -#define S3C2410_DCON_CH2_I2SSDO (0<<24) -#define S3C2410_DCON_CH2_I2SSDI (1<<24) -#define S3C2410_DCON_CH2_SDI (2<<24) -#define S3C2410_DCON_CH2_TIMER (3<<24) -#define S3C2410_DCON_CH2_USBEP3 (4<<24) +#define S3C2410_DCON_CH2_I2SSDO (0 << 24) +#define S3C2410_DCON_CH2_I2SSDI (1 << 24) +#define S3C2410_DCON_CH2_SDI (2 << 24) +#define S3C2410_DCON_CH2_TIMER (3 << 24) +#define S3C2410_DCON_CH2_USBEP3 (4 << 24) -#define S3C2410_DCON_CH3_UART2 (0<<24) -#define S3C2410_DCON_CH3_SDI (1<<24) -#define S3C2410_DCON_CH3_SPI (2<<24) -#define S3C2410_DCON_CH3_TIMER (3<<24) -#define S3C2410_DCON_CH3_USBEP4 (4<<24) +#define S3C2410_DCON_CH3_UART2 (0 << 24) +#define S3C2410_DCON_CH3_SDI (1 << 24) +#define S3C2410_DCON_CH3_SPI (2 << 24) +#define S3C2410_DCON_CH3_TIMER (3 << 24) +#define S3C2410_DCON_CH3_USBEP4 (4 << 24) #define S3C2410_DCON_SRCSHIFT (24) -#define S3C2410_DCON_SRCMASK (7<<24) +#define S3C2410_DCON_SRCMASK (7 << 24) -#define S3C2410_DCON_BYTE (0<<20) -#define S3C2410_DCON_HALFWORD (1<<20) -#define S3C2410_DCON_WORD (2<<20) +#define S3C2410_DCON_BYTE (0 << 20) +#define S3C2410_DCON_HALFWORD (1 << 20) +#define S3C2410_DCON_WORD (2 << 20) -#define S3C2410_DCON_AUTORELOAD (0<<22) -#define S3C2410_DCON_NORELOAD (1<<22) -#define S3C2410_DCON_HWTRIG (1<<23) +#define S3C2410_DCON_AUTORELOAD (0 << 22) +#define S3C2410_DCON_NORELOAD (1 << 22) +#define S3C2410_DCON_HWTRIG (1 << 23) #ifdef CONFIG_CPU_S3C2440 -#define S3C2440_DIDSTC_CHKINT (1<<2) -#define S3C2440_DCON_CH0_I2SSDO (5<<24) -#define S3C2440_DCON_CH0_PCMIN (6<<24) +#define S3C2440_DIDSTC_CHKINT (1 << 2) -#define S3C2440_DCON_CH1_PCMOUT (5<<24) -#define S3C2440_DCON_CH1_SDI (6<<24) +#define S3C2440_DCON_CH0_I2SSDO (5 << 24) +#define S3C2440_DCON_CH0_PCMIN (6 << 24) -#define S3C2440_DCON_CH2_PCMIN (5<<24) -#define S3C2440_DCON_CH2_MICIN (6<<24) +#define S3C2440_DCON_CH1_PCMOUT (5 << 24) +#define S3C2440_DCON_CH1_SDI (6 << 24) -#define S3C2440_DCON_CH3_MICIN (5<<24) -#define S3C2440_DCON_CH3_PCMOUT (6<<24) -#endif +#define S3C2440_DCON_CH2_PCMIN (5 << 24) +#define S3C2440_DCON_CH2_MICIN (6 << 24) + +#define S3C2440_DCON_CH3_MICIN (5 << 24) +#define S3C2440_DCON_CH3_PCMOUT (6 << 24) +#endif /* CONFIG_CPU_S3C2440 */ #ifdef CONFIG_CPU_S3C2412 -#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1) +#define S3C2412_DMAREQSEL_SRC(x) ((x) << 1) #define S3C2412_DMAREQSEL_HW (1) @@ -115,10 +117,11 @@ #define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) #define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) #define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) +#endif /* CONFIG_CPU_S3C2412 */ -#endif +#ifdef CONFIG_CPU_S3C2443 -#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) +#define S3C2443_DMAREQSEL_SRC(x) ((x) << 1) #define S3C2443_DMAREQSEL_HW (1) @@ -141,5 +144,8 @@ #define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) #define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) #define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) -#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) +#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) #define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) +#endif /* CONFIG_CPU_S3C2443 */ + +#endif /* __ASM_PLAT_REGS_DMA_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-iis.h b/arch/arm/plat-samsung/include/plat/regs-iis.h new file mode 100644 index 000000000000..a18d35e7a735 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-iis.h @@ -0,0 +1,70 @@ +/* arch/arm/plat-samsung/include/plat/regs-iis.h + * + * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> + * http://www.simtec.co.uk/products/SWLINUX/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 IIS register definition +*/ + +#ifndef __ASM_ARCH_REGS_IIS_H +#define __ASM_ARCH_REGS_IIS_H + +#define S3C2410_IISCON (0x00) + +#define S3C2410_IISCON_LRINDEX (1 << 8) +#define S3C2410_IISCON_TXFIFORDY (1 << 7) +#define S3C2410_IISCON_RXFIFORDY (1 << 6) +#define S3C2410_IISCON_TXDMAEN (1 << 5) +#define S3C2410_IISCON_RXDMAEN (1 << 4) +#define S3C2410_IISCON_TXIDLE (1 << 3) +#define S3C2410_IISCON_RXIDLE (1 << 2) +#define S3C2410_IISCON_PSCEN (1 << 1) +#define S3C2410_IISCON_IISEN (1 << 0) + +#define S3C2410_IISMOD (0x04) + +#define S3C2440_IISMOD_MPLL (1 << 9) +#define S3C2410_IISMOD_SLAVE (1 << 8) +#define S3C2410_IISMOD_NOXFER (0 << 6) +#define S3C2410_IISMOD_RXMODE (1 << 6) +#define S3C2410_IISMOD_TXMODE (2 << 6) +#define S3C2410_IISMOD_TXRXMODE (3 << 6) +#define S3C2410_IISMOD_LR_LLOW (0 << 5) +#define S3C2410_IISMOD_LR_RLOW (1 << 5) +#define S3C2410_IISMOD_IIS (0 << 4) +#define S3C2410_IISMOD_MSB (1 << 4) +#define S3C2410_IISMOD_8BIT (0 << 3) +#define S3C2410_IISMOD_16BIT (1 << 3) +#define S3C2410_IISMOD_BITMASK (1 << 3) +#define S3C2410_IISMOD_256FS (0 << 2) +#define S3C2410_IISMOD_384FS (1 << 2) +#define S3C2410_IISMOD_16FS (0 << 0) +#define S3C2410_IISMOD_32FS (1 << 0) +#define S3C2410_IISMOD_48FS (2 << 0) +#define S3C2410_IISMOD_FS_MASK (3 << 0) + +#define S3C2410_IISPSR (0x08) + +#define S3C2410_IISPSR_INTMASK (31 << 5) +#define S3C2410_IISPSR_INTSHIFT (5) +#define S3C2410_IISPSR_EXTMASK (31 << 0) +#define S3C2410_IISPSR_EXTSHFIT (0) + +#define S3C2410_IISFCON (0x0c) + +#define S3C2410_IISFCON_TXDMA (1 << 15) +#define S3C2410_IISFCON_RXDMA (1 << 14) +#define S3C2410_IISFCON_TXENABLE (1 << 13) +#define S3C2410_IISFCON_RXENABLE (1 << 12) +#define S3C2410_IISFCON_TXMASK (0x3f << 6) +#define S3C2410_IISFCON_TXSHIFT (6) +#define S3C2410_IISFCON_RXMASK (0x3f) +#define S3C2410_IISFCON_RXSHIFT (0) + +#define S3C2410_IISFIFO (0x10) + +#endif /* __ASM_ARCH_REGS_IIS_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-spi.h b/arch/arm/plat-samsung/include/plat/regs-spi.h new file mode 100644 index 000000000000..552fe7cfe281 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-spi.h @@ -0,0 +1,48 @@ +/* arch/arm/plat-samsung/include/plat/regs-spi.h + * + * Copyright (c) 2004 Fetron GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * S3C2410 SPI register definition +*/ + +#ifndef __ASM_ARCH_REGS_SPI_H +#define __ASM_ARCH_REGS_SPI_H + +#define S3C2410_SPI1 (0x20) +#define S3C2412_SPI1 (0x100) + +#define S3C2410_SPCON (0x00) + +#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */ +#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */ +#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */ +#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */ +#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */ +#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */ +#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */ + +#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */ +#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */ + +#define S3C2410_SPSTA (0x04) + +#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */ +#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */ +#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */ +#define S3C2412_SPSTA_READY_ORG (1 << 3) + +#define S3C2410_SPPIN (0x08) + +#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */ +#define S3C2410_SPPIN_RESERVED (1 << 1) +#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */ + +#define S3C2410_SPPRE (0x0C) +#define S3C2410_SPTDAT (0x10) +#define S3C2410_SPRDAT (0x14) + +#endif /* __ASM_ARCH_REGS_SPI_H */ diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-samsung/include/plat/regs-srom.h index f121ab5e76cb..9b6729c81cda 100644 --- a/arch/arm/plat-s5p/include/plat/regs-srom.h +++ b/arch/arm/plat-samsung/include/plat/regs-srom.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h +/* linux/arch/arm/plat-samsung/include/plat/regs-srom.h * * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com @@ -10,8 +10,8 @@ * published by the Free Software Foundation. */ -#ifndef __ASM_PLAT_S5P_REGS_SROM_H -#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__ +#ifndef __PLAT_SAMSUNG_REGS_SROM_H +#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__ #include <mach/map.h> @@ -51,4 +51,4 @@ #define S5P_SROM_BCX__TCOS__SHIFT 24 #define S5P_SROM_BCX__TACS__SHIFT 28 -#endif /* __ASM_PLAT_S5P_REGS_SROM_H */ +#endif /* __PLAT_SAMSUNG_REGS_SROM_H */ diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h b/arch/arm/plat-samsung/include/plat/regs-udc.h index f0dd4a41b37b..4003d3dab4e7 100644 --- a/arch/arm/plat-s3c24xx/include/plat/regs-udc.h +++ b/arch/arm/plat-samsung/include/plat/regs-udc.h @@ -1,4 +1,4 @@ -/* arch/arm/mach-s3c2410/include/mach/regs-udc.h +/* arch/arm/plat-samsung/include/plat/regs-udc.h * * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> * @@ -75,79 +75,77 @@ #define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198) #define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c) -#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7) +#define S3C2410_UDC_FUNCADDR_UPDATE (1 << 7) -#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W -#define S3C2410_UDC_PWR_RESET (1<<3) // R -#define S3C2410_UDC_PWR_RESUME (1<<2) // R/W -#define S3C2410_UDC_PWR_SUSPEND (1<<1) // R -#define S3C2410_UDC_PWR_ENSUSPEND (1<<0) // R/W +#define S3C2410_UDC_PWR_ISOUP (1 << 7) /* R/W */ +#define S3C2410_UDC_PWR_RESET (1 << 3) /* R */ +#define S3C2410_UDC_PWR_RESUME (1 << 2) /* R/W */ +#define S3C2410_UDC_PWR_SUSPEND (1 << 1) /* R */ +#define S3C2410_UDC_PWR_ENSUSPEND (1 << 0) /* R/W */ -#define S3C2410_UDC_PWR_DEFAULT 0x00 +#define S3C2410_UDC_PWR_DEFAULT (0x00) -#define S3C2410_UDC_INT_EP4 (1<<4) // R/W (clear only) -#define S3C2410_UDC_INT_EP3 (1<<3) // R/W (clear only) -#define S3C2410_UDC_INT_EP2 (1<<2) // R/W (clear only) -#define S3C2410_UDC_INT_EP1 (1<<1) // R/W (clear only) -#define S3C2410_UDC_INT_EP0 (1<<0) // R/W (clear only) +#define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */ +#define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */ +#define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */ +#define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */ +#define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */ -#define S3C2410_UDC_USBINT_RESET (1<<2) // R/W (clear only) -#define S3C2410_UDC_USBINT_RESUME (1<<1) // R/W (clear only) -#define S3C2410_UDC_USBINT_SUSPEND (1<<0) // R/W (clear only) +#define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */ +#define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */ +#define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */ -#define S3C2410_UDC_INTE_EP4 (1<<4) // R/W -#define S3C2410_UDC_INTE_EP3 (1<<3) // R/W -#define S3C2410_UDC_INTE_EP2 (1<<2) // R/W -#define S3C2410_UDC_INTE_EP1 (1<<1) // R/W -#define S3C2410_UDC_INTE_EP0 (1<<0) // R/W - -#define S3C2410_UDC_USBINTE_RESET (1<<2) // R/W -#define S3C2410_UDC_USBINTE_SUSPEND (1<<0) // R/W +#define S3C2410_UDC_INTE_EP4 (1 << 4) /* R/W */ +#define S3C2410_UDC_INTE_EP3 (1 << 3) /* R/W */ +#define S3C2410_UDC_INTE_EP2 (1 << 2) /* R/W */ +#define S3C2410_UDC_INTE_EP1 (1 << 1) /* R/W */ +#define S3C2410_UDC_INTE_EP0 (1 << 0) /* R/W */ +#define S3C2410_UDC_USBINTE_RESET (1 << 2) /* R/W */ +#define S3C2410_UDC_USBINTE_SUSPEND (1 << 0) /* R/W */ #define S3C2410_UDC_INDEX_EP0 (0x00) -#define S3C2410_UDC_INDEX_EP1 (0x01) // ?? -#define S3C2410_UDC_INDEX_EP2 (0x02) // ?? -#define S3C2410_UDC_INDEX_EP3 (0x03) // ?? -#define S3C2410_UDC_INDEX_EP4 (0x04) // ?? - -#define S3C2410_UDC_ICSR1_CLRDT (1<<6) // R/W -#define S3C2410_UDC_ICSR1_SENTSTL (1<<5) // R/W (clear only) -#define S3C2410_UDC_ICSR1_SENDSTL (1<<4) // R/W -#define S3C2410_UDC_ICSR1_FFLUSH (1<<3) // W (set only) -#define S3C2410_UDC_ICSR1_UNDRUN (1<<2) // R/W (clear only) -#define S3C2410_UDC_ICSR1_PKTRDY (1<<0) // R/W (set only) - -#define S3C2410_UDC_ICSR2_AUTOSET (1<<7) // R/W -#define S3C2410_UDC_ICSR2_ISO (1<<6) // R/W -#define S3C2410_UDC_ICSR2_MODEIN (1<<5) // R/W -#define S3C2410_UDC_ICSR2_DMAIEN (1<<4) // R/W - -#define S3C2410_UDC_OCSR1_CLRDT (1<<7) // R/W -#define S3C2410_UDC_OCSR1_SENTSTL (1<<6) // R/W (clear only) -#define S3C2410_UDC_OCSR1_SENDSTL (1<<5) // R/W -#define S3C2410_UDC_OCSR1_FFLUSH (1<<4) // R/W -#define S3C2410_UDC_OCSR1_DERROR (1<<3) // R -#define S3C2410_UDC_OCSR1_OVRRUN (1<<2) // R/W (clear only) -#define S3C2410_UDC_OCSR1_PKTRDY (1<<0) // R/W (clear only) - -#define S3C2410_UDC_OCSR2_AUTOCLR (1<<7) // R/W -#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W -#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W - -#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0) -#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1) -#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2) -#define S3C2410_UDC_EP0_CSR_DE (1<<3) -#define S3C2410_UDC_EP0_CSR_SE (1<<4) -#define S3C2410_UDC_EP0_CSR_SENDSTL (1<<5) -#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1<<6) -#define S3C2410_UDC_EP0_CSR_SSE (1<<7) - -#define S3C2410_UDC_MAXP_8 (1<<0) -#define S3C2410_UDC_MAXP_16 (1<<1) -#define S3C2410_UDC_MAXP_32 (1<<2) -#define S3C2410_UDC_MAXP_64 (1<<3) - +#define S3C2410_UDC_INDEX_EP1 (0x01) +#define S3C2410_UDC_INDEX_EP2 (0x02) +#define S3C2410_UDC_INDEX_EP3 (0x03) +#define S3C2410_UDC_INDEX_EP4 (0x04) + +#define S3C2410_UDC_ICSR1_CLRDT (1 << 6) /* R/W */ +#define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */ +#define S3C2410_UDC_ICSR1_SENDSTL (1 << 4) /* R/W */ +#define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */ +#define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */ +#define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */ + +#define S3C2410_UDC_ICSR2_AUTOSET (1 << 7) /* R/W */ +#define S3C2410_UDC_ICSR2_ISO (1 << 6) /* R/W */ +#define S3C2410_UDC_ICSR2_MODEIN (1 << 5) /* R/W */ +#define S3C2410_UDC_ICSR2_DMAIEN (1 << 4) /* R/W */ + +#define S3C2410_UDC_OCSR1_CLRDT (1 << 7) /* R/W */ +#define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */ +#define S3C2410_UDC_OCSR1_SENDSTL (1 << 5) /* R/W */ +#define S3C2410_UDC_OCSR1_FFLUSH (1 << 4) /* R/W */ +#define S3C2410_UDC_OCSR1_DERROR (1 << 3) /* R */ +#define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */ +#define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */ + +#define S3C2410_UDC_OCSR2_AUTOCLR (1 << 7) /* R/W */ +#define S3C2410_UDC_OCSR2_ISO (1 << 6) /* R/W */ +#define S3C2410_UDC_OCSR2_DMAIEN (1 << 5) /* R/W */ + +#define S3C2410_UDC_EP0_CSR_OPKRDY (1 << 0) +#define S3C2410_UDC_EP0_CSR_IPKRDY (1 << 1) +#define S3C2410_UDC_EP0_CSR_SENTSTL (1 << 2) +#define S3C2410_UDC_EP0_CSR_DE (1 << 3) +#define S3C2410_UDC_EP0_CSR_SE (1 << 4) +#define S3C2410_UDC_EP0_CSR_SENDSTL (1 << 5) +#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1 << 6) +#define S3C2410_UDC_EP0_CSR_SSE (1 << 7) + +#define S3C2410_UDC_MAXP_8 (1 << 0) +#define S3C2410_UDC_MAXP_16 (1 << 1) +#define S3C2410_UDC_MAXP_32 (1 << 2) +#define S3C2410_UDC_MAXP_64 (1 << 3) #endif diff --git a/arch/arm/plat-s5p/include/plat/reset.h b/arch/arm/plat-samsung/include/plat/reset.h index 335e97812eed..32ca5179c6e1 100644 --- a/arch/arm/plat-s5p/include/plat/reset.h +++ b/arch/arm/plat-samsung/include/plat/reset.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/include/plat/reset.h +/* linux/arch/arm/plat-samsung/include/plat/reset.h * * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com/ @@ -8,9 +8,9 @@ * published by the Free Software Foundation. */ -#ifndef __ASM_PLAT_S5P_RESET_H -#define __ASM_PLAT_S5P_RESET_H __FILE__ +#ifndef __PLAT_SAMSUNG_RESET_H +#define __PLAT_SAMSUNG_RESET_H __FILE__ extern void (*s5p_reset_hook)(void); -#endif /* __ASM_PLAT_S5P_RESET_H */ +#endif /* __PLAT_SAMSUNG_RESET_H */ diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h index 82ab4aad1bbe..3986497dd3f7 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h +++ b/arch/arm/plat-samsung/include/plat/s3c2410.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/s3c2410.h +/* linux/arch/arm/plat-samsung/include/plat/s3c2410.h * * Copyright (c) 2004 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h index bb15d3b68be5..5bcfd143ba16 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h +++ b/arch/arm/plat-samsung/include/plat/s3c2412.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/s3c2412.h +/* linux/arch/arm/plat-samsung/include/plat/s3c2412.h * * Copyright (c) 2006 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h index dc3c0907d221..a764f8503f52 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2416.h +++ b/arch/arm/plat-samsung/include/plat/s3c2416.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h +/* linux/arch/arm/plat-samsung/include/plat/s3c2416.h * * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com> * diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h index a19715feb798..4b2ac9a272b2 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h +++ b/arch/arm/plat-samsung/include/plat/s3c2443.h @@ -1,4 +1,4 @@ -/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h +/* linux/arch/arm/plat-samsung/include/plat/s3c2443.h * * Copyright (c) 2004-2005 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h b/arch/arm/plat-samsung/include/plat/s3c244x.h index 89e8d0a25f87..ea0c961b7603 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h +++ b/arch/arm/plat-samsung/include/plat/s3c244x.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s3c24xx/include/plat/s3c244x.h +/* linux/arch/arm/plat-samsung/include/plat/s3c244x.h * * Copyright (c) 2004-2005 Simtec Electronics * Ben Dooks <ben@simtec.co.uk> diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h b/arch/arm/plat-samsung/include/plat/s3c6400.h index f86958d05352..37d428aaaebb 100644 --- a/arch/arm/mach-s3c64xx/include/mach/s3c6400.h +++ b/arch/arm/plat-samsung/include/plat/s3c6400.h @@ -1,4 +1,4 @@ -/* arch/arm/mach-s3c64xx/include/macht/s3c6400.h +/* linux/arch/arm/plat-samsung/include/plat/s3c6400.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/mach-s3c64xx/include/mach/s3c6410.h b/arch/arm/plat-samsung/include/plat/s3c6410.h index 24f1141ffcb7..20a6675b9d17 100644 --- a/arch/arm/mach-s3c64xx/include/mach/s3c6410.h +++ b/arch/arm/plat-samsung/include/plat/s3c6410.h @@ -1,4 +1,4 @@ -/* arch/arm/mach-s3c64xx/include/mach/s3c6410.h +/* linux/arch/arm/plat-samsung/include/plat/s3c6410.h * * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h index 769b5bdfb046..984bf9e7bc89 100644 --- a/arch/arm/plat-s5p/include/plat/s5p-clock.h +++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h +/* linux/arch/arm/plat-samsung/include/plat/s5p-clock.h * * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. * http://www.samsung.com diff --git a/arch/arm/plat-s5p/include/plat/s5p-time.h b/arch/arm/plat-samsung/include/plat/s5p-time.h index 575e88109db8..3a70aebc9205 100644 --- a/arch/arm/plat-s5p/include/plat/s5p-time.h +++ b/arch/arm/plat-samsung/include/plat/s5p-time.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/include/plat/s5p-time.h +/* linux/arch/arm/plat-samsung/include/plat/s5p-time.h * * Copyright 2011 Samsung Electronics Co., Ltd. * http://www.samsung.com/ diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-samsung/include/plat/s5p6440.h index 528585d2cafc..bf85ebbb4fbc 100644 --- a/arch/arm/plat-s5p/include/plat/s5p6440.h +++ b/arch/arm/plat-samsung/include/plat/s5p6440.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s5p/include/plat/s5p6440.h +/* linux/arch/arm/plat-samsung/include/plat/s5p6440.h * * Copyright (c) 2009 Samsung Electronics Co., Ltd. * http://www.samsung.com/ diff --git a/arch/arm/plat-s5p/include/plat/s5p6450.h b/arch/arm/plat-samsung/include/plat/s5p6450.h index 640a41c26be3..da25f9a1c54a 100644 --- a/arch/arm/plat-s5p/include/plat/s5p6450.h +++ b/arch/arm/plat-samsung/include/plat/s5p6450.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s5p/include/plat/s5p6450.h +/* linux/arch/arm/plat-samsung/include/plat/s5p6450.h * * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com diff --git a/arch/arm/plat-s5p/include/plat/s5pc100.h b/arch/arm/plat-samsung/include/plat/s5pc100.h index 5f6099dd7cad..9a21aeaaf452 100644 --- a/arch/arm/plat-s5p/include/plat/s5pc100.h +++ b/arch/arm/plat-samsung/include/plat/s5pc100.h @@ -1,4 +1,4 @@ -/* arch/arm/plat-s5p/include/plat/s5pc100.h +/* linux/arch/arm/plat-samsung/include/plat/s5pc100.h * * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com/ diff --git a/arch/arm/plat-s5p/include/plat/s5pv210.h b/arch/arm/plat-samsung/include/plat/s5pv210.h index 6c93a0c78100..b4bc6be77072 100644 --- a/arch/arm/plat-s5p/include/plat/s5pv210.h +++ b/arch/arm/plat-samsung/include/plat/s5pv210.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/include/plat/s5pv210.h +/* linux/arch/arm/plat-samsung/include/plat/s5pv210.h * * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com/ diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 4a6552066c7e..e7b3c752e919 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h @@ -55,10 +55,6 @@ enum clk_types { * cd_type == S3C_SDHCI_CD_GPIO * @ext_cd_gpio_invert: invert values for external CD gpio line * @cfg_gpio: Configure the GPIO for a specific card bit-width - * @cfg_card: Configure the interface for a specific card and speed. This - * is necessary the controllers and/or GPIO blocks require the - * changing of driver-strength and other controls dependent on - * the card and speed of operation. * * Initialisation data specific to either the machine or the platform * for the device driver to use or call-back when configuring gpio or @@ -80,10 +76,6 @@ struct s3c_sdhci_platdata { int state)); void (*cfg_gpio)(struct platform_device *dev, int width); - void (*cfg_card)(struct platform_device *dev, - void __iomem *regbase, - struct mmc_ios *ios, - struct mmc_card *card); }; /* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data @@ -139,17 +131,11 @@ extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); #ifdef CONFIG_S3C2416_SETUP_SDHCI extern char *s3c2416_hsmmc_clksrcs[4]; -extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card); - static inline void s3c2416_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card; #endif /* CONFIG_S3C_DEV_HSMMC */ } @@ -158,7 +144,6 @@ static inline void s3c2416_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card; #endif /* CONFIG_S3C_DEV_HSMMC1 */ } @@ -172,17 +157,11 @@ static inline void s3c2416_default_sdhci1(void) { } #ifdef CONFIG_S3C64XX_SETUP_SDHCI extern char *s3c64xx_hsmmc_clksrcs[4]; -extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card); - static inline void s3c6400_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; #endif } @@ -191,7 +170,6 @@ static inline void s3c6400_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; #endif } @@ -200,21 +178,14 @@ static inline void s3c6400_default_sdhci2(void) #ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; - s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; #endif } -extern void s3c6410_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card); - static inline void s3c6410_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; #endif } @@ -223,7 +194,6 @@ static inline void s3c6410_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; #endif } @@ -232,7 +202,6 @@ static inline void s3c6410_default_sdhci2(void) #ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s3c64xx_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; - s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci_cfg_card; #endif } @@ -251,17 +220,11 @@ static inline void s3c6400_default_sdhci2(void) { } #ifdef CONFIG_S5PC100_SETUP_SDHCI extern char *s5pc100_hsmmc_clksrcs[4]; -extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card); - static inline void s5pc100_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; #endif } @@ -270,7 +233,6 @@ static inline void s5pc100_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; #endif } @@ -279,7 +241,6 @@ static inline void s5pc100_default_sdhci2(void) #ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; - s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; #endif } @@ -295,17 +256,11 @@ static inline void s5pc100_default_sdhci2(void) { } #ifdef CONFIG_S5PV210_SETUP_SDHCI extern char *s5pv210_hsmmc_clksrcs[4]; -extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card); - static inline void s5pv210_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; #endif } @@ -314,7 +269,6 @@ static inline void s5pv210_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; #endif } @@ -323,7 +277,6 @@ static inline void s5pv210_default_sdhci2(void) #ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; - s3c_hsmmc2_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; #endif } @@ -332,7 +285,6 @@ static inline void s5pv210_default_sdhci3(void) #ifdef CONFIG_S3C_DEV_HSMMC3 s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio; - s3c_hsmmc3_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; #endif } @@ -348,17 +300,11 @@ static inline void s5pv210_default_sdhci3(void) { } #ifdef CONFIG_EXYNOS4_SETUP_SDHCI extern char *exynos4_hsmmc_clksrcs[4]; -extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, - void __iomem *r, - struct mmc_ios *ios, - struct mmc_card *card); - static inline void exynos4_default_sdhci0(void) { #ifdef CONFIG_S3C_DEV_HSMMC s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio; - s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } @@ -367,7 +313,6 @@ static inline void exynos4_default_sdhci1(void) #ifdef CONFIG_S3C_DEV_HSMMC1 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio; - s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } @@ -376,7 +321,6 @@ static inline void exynos4_default_sdhci2(void) #ifdef CONFIG_S3C_DEV_HSMMC2 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio; - s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } @@ -385,7 +329,6 @@ static inline void exynos4_default_sdhci3(void) #ifdef CONFIG_S3C_DEV_HSMMC3 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs; s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio; - s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card; #endif } diff --git a/arch/arm/plat-s5p/include/plat/sysmmu.h b/arch/arm/plat-samsung/include/plat/sysmmu.h index bf5283c2a19d..5fe8ee01a5ba 100644 --- a/arch/arm/plat-s5p/include/plat/sysmmu.h +++ b/arch/arm/plat-samsung/include/plat/sysmmu.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/include/plat/sysmmu.h +/* linux/arch/arm/plat-samsung/include/plat/sysmmu.h * * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com @@ -10,8 +10,8 @@ * published by the Free Software Foundation. */ -#ifndef __ASM__PLAT_SYSMMU_H -#define __ASM__PLAT_SYSMMU_H __FILE__ +#ifndef __PLAT_SAMSUNG_SYSMMU_H +#define __PLAT_SAMSUNG_SYSMMU_H __FILE__ enum S5P_SYSMMU_INTERRUPT_TYPE { SYSMMU_PAGEFAULT, diff --git a/arch/arm/plat-s5p/include/plat/system-reset.h b/arch/arm/plat-samsung/include/plat/system-reset.h index f307f34e6422..a448e990964d 100644 --- a/arch/arm/plat-s5p/include/plat/system-reset.h +++ b/arch/arm/plat-samsung/include/plat/system-reset.h @@ -1,4 +1,4 @@ -/* linux/arch/arm/plat-s5p/include/plat/system-reset.h +/* linux/arch/arm/plat-samsung/include/plat/system-reset.h * * Copyright (c) 2010 Samsung Electronics Co., Ltd. * http://www.samsung.com diff --git a/arch/arm/plat-samsung/include/plat/tv-core.h b/arch/arm/plat-samsung/include/plat/tv-core.h new file mode 100644 index 000000000000..3bc34f3ce28f --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/tv-core.h @@ -0,0 +1,44 @@ +/* + * arch/arm/plat-samsung/include/plat/tv.h + * + * Copyright 2011 Samsung Electronics Co., Ltd. + * Tomasz Stanislawski <t.stanislaws@samsung.com> + * + * Samsung TV driver core functions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SAMSUNG_PLAT_TV_H +#define __SAMSUNG_PLAT_TV_H __FILE__ + +/* + * These functions are only for use with the core support code, such as + * the CPU-specific initialization code. + */ + +/* Re-define device name to differentiate the subsystem in various SoCs. */ +static inline void s5p_hdmi_setname(char *name) +{ +#ifdef CONFIG_S5P_DEV_TV + s5p_device_hdmi.name = name; +#endif +} + +static inline void s5p_mixer_setname(char *name) +{ +#ifdef CONFIG_S5P_DEV_TV + s5p_device_mixer.name = name; +#endif +} + +static inline void s5p_sdo_setname(char *name) +{ +#ifdef CONFIG_S5P_DEV_TV + s5p_device_sdo.name = name; +#endif +} + +#endif /* __SAMSUNG_PLAT_TV_H */ diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-samsung/include/plat/udc.h index f63884242506..8c22d586befb 100644 --- a/arch/arm/plat-s3c24xx/include/plat/udc.h +++ b/arch/arm/plat-samsung/include/plat/udc.h @@ -1,4 +1,4 @@ -/* arch/arm/mach-s3c2410/include/mach/udc.h +/* arch/arm/plat-samsung/include/plat/udc.h * * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> * @@ -26,7 +26,7 @@ enum s3c2410_udc_cmd_e { struct s3c2410_udc_mach_info { void (*udc_command)(enum s3c2410_udc_cmd_e); - void (*vbus_draw)(unsigned int ma); + void (*vbus_draw)(unsigned int ma); unsigned int pullup_pin; unsigned int pullup_pin_inverted; diff --git a/arch/arm/plat-s5p/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h index 6dd6bcfca3ce..959bcdb03a25 100644 --- a/arch/arm/plat-s5p/include/plat/usb-phy.h +++ b/arch/arm/plat-samsung/include/plat/usb-phy.h @@ -8,8 +8,8 @@ * option) any later version. */ -#ifndef __PLAT_S5P_USB_PHY_H -#define __PLAT_S5P_USB_PHY_H +#ifndef __PLAT_SAMSUNG_USB_PHY_H +#define __PLAT_SAMSUNG_USB_PHY_H __FILE__ enum s5p_usb_phy_type { S5P_USB_PHY_DEVICE, @@ -19,4 +19,4 @@ enum s5p_usb_phy_type { extern int s5p_usb_phy_init(struct platform_device *pdev, int type); extern int s5p_usb_phy_exit(struct platform_device *pdev, int type); -#endif /* __PLAT_S5P_REGS_USB_PHY_H */ +#endif /* __PLAT_SAMSUNG_USB_PHY_H */ diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c index 6de1a3825927..4c9a20734fe3 100644 --- a/arch/arm/plat-samsung/platformdata.c +++ b/arch/arm/plat-samsung/platformdata.c @@ -50,8 +50,6 @@ void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd, set->max_width = pd->max_width; if (pd->cfg_gpio) set->cfg_gpio = pd->cfg_gpio; - if (pd->cfg_card) - set->cfg_card = pd->cfg_card; if (pd->host_caps) set->host_caps |= pd->host_caps; if (pd->clk_type) diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index 96528200eb79..4be016eaa6db 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -28,13 +28,13 @@ #define OFFS_DAT (0x04) #define OFFS_UP (0x08) -static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip) +static void samsung_gpio_pm_1bit_save(struct samsung_gpio_chip *chip) { chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); } -static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip) +static void samsung_gpio_pm_1bit_resume(struct samsung_gpio_chip *chip) { void __iomem *base = chip->base; u32 old_gpcon = __raw_readl(base + OFFS_CON); @@ -60,12 +60,12 @@ static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip) chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); } -struct s3c_gpio_pm s3c_gpio_pm_1bit = { - .save = s3c_gpio_pm_1bit_save, - .resume = s3c_gpio_pm_1bit_resume, +struct samsung_gpio_pm samsung_gpio_pm_1bit = { + .save = samsung_gpio_pm_1bit_save, + .resume = samsung_gpio_pm_1bit_resume, }; -static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip) +static void samsung_gpio_pm_2bit_save(struct samsung_gpio_chip *chip) { chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); @@ -95,7 +95,7 @@ static inline int is_out(unsigned long con) } /** - * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank + * samsung_gpio_pm_2bit_resume() - restore the given GPIO bank * @chip: The chip information to resume. * * Restore one of the GPIO banks that was saved during suspend. This is @@ -121,7 +121,7 @@ static inline int is_out(unsigned long con) * [1] this assumes that writing to a pin DAT whilst in SFN will set the * state for when it is next output. */ -static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip) +static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip) { void __iomem *base = chip->base; u32 old_gpcon = __raw_readl(base + OFFS_CON); @@ -187,13 +187,13 @@ static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip) chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); } -struct s3c_gpio_pm s3c_gpio_pm_2bit = { - .save = s3c_gpio_pm_2bit_save, - .resume = s3c_gpio_pm_2bit_resume, +struct samsung_gpio_pm samsung_gpio_pm_2bit = { + .save = samsung_gpio_pm_2bit_save, + .resume = samsung_gpio_pm_2bit_resume, }; #if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) -static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip) +static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip) { chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); @@ -203,7 +203,7 @@ static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip) chip->pm_save[0] = __raw_readl(chip->base - 4); } -static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) +static u32 samsung_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) { u32 old, new, mask; u32 change_mask = 0x0; @@ -242,14 +242,14 @@ static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) return change_mask; } -static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index) +static void samsung_gpio_pm_4bit_con(struct samsung_gpio_chip *chip, int index) { void __iomem *con = chip->base + (index * 4); u32 old_gpcon = __raw_readl(con); u32 gps_gpcon = chip->pm_save[index + 1]; u32 gpcon, mask; - mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon); + mask = samsung_gpio_pm_4bit_mask(old_gpcon, gps_gpcon); gpcon = old_gpcon & ~mask; gpcon |= gps_gpcon & mask; @@ -257,7 +257,7 @@ static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index) __raw_writel(gpcon, con); } -static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) +static void samsung_gpio_pm_4bit_resume(struct samsung_gpio_chip *chip) { void __iomem *base = chip->base; u32 old_gpcon[2]; @@ -269,10 +269,10 @@ static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) old_gpcon[0] = 0; old_gpcon[1] = __raw_readl(base + OFFS_CON); - s3c_gpio_pm_4bit_con(chip, 0); + samsung_gpio_pm_4bit_con(chip, 0); if (chip->chip.ngpio > 8) { old_gpcon[0] = __raw_readl(base - 4); - s3c_gpio_pm_4bit_con(chip, -1); + samsung_gpio_pm_4bit_con(chip, -1); } /* Now change the configurations that require DAT,CON */ @@ -298,19 +298,19 @@ static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) old_gpdat, gps_gpdat); } -struct s3c_gpio_pm s3c_gpio_pm_4bit = { - .save = s3c_gpio_pm_4bit_save, - .resume = s3c_gpio_pm_4bit_resume, +struct samsung_gpio_pm samsung_gpio_pm_4bit = { + .save = samsung_gpio_pm_4bit_save, + .resume = samsung_gpio_pm_4bit_resume, }; #endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */ /** - * s3c_pm_save_gpio() - save gpio chip data for suspend + * samsung_pm_save_gpio() - save gpio chip data for suspend * @ourchip: The chip for suspend. */ -static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip) +static void samsung_pm_save_gpio(struct samsung_gpio_chip *ourchip) { - struct s3c_gpio_pm *pm = ourchip->pm; + struct samsung_gpio_pm *pm = ourchip->pm; if (pm == NULL || pm->save == NULL) S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); @@ -319,24 +319,24 @@ static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip) } /** - * s3c_pm_save_gpios() - Save the state of the GPIO banks. + * samsung_pm_save_gpios() - Save the state of the GPIO banks. * * For all the GPIO banks, save the state of each one ready for going * into a suspend mode. */ -void s3c_pm_save_gpios(void) +void samsung_pm_save_gpios(void) { - struct s3c_gpio_chip *ourchip; + struct samsung_gpio_chip *ourchip; unsigned int gpio_nr; for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { - ourchip = s3c_gpiolib_getchip(gpio_nr); + ourchip = samsung_gpiolib_getchip(gpio_nr); if (!ourchip) { gpio_nr++; continue; } - s3c_pm_save_gpio(ourchip); + samsung_pm_save_gpio(ourchip); S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n", ourchip->chip.label, @@ -351,12 +351,12 @@ void s3c_pm_save_gpios(void) } /** - * s3c_pm_resume_gpio() - restore gpio chip data after suspend + * samsung_pm_resume_gpio() - restore gpio chip data after suspend * @ourchip: The suspended chip. */ -static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip) +static void samsung_pm_resume_gpio(struct samsung_gpio_chip *ourchip) { - struct s3c_gpio_pm *pm = ourchip->pm; + struct samsung_gpio_pm *pm = ourchip->pm; if (pm == NULL || pm->resume == NULL) S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); @@ -364,19 +364,19 @@ static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip) pm->resume(ourchip); } -void s3c_pm_restore_gpios(void) +void samsung_pm_restore_gpios(void) { - struct s3c_gpio_chip *ourchip; + struct samsung_gpio_chip *ourchip; unsigned int gpio_nr; for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { - ourchip = s3c_gpiolib_getchip(gpio_nr); + ourchip = samsung_gpiolib_getchip(gpio_nr); if (!ourchip) { gpio_nr++; continue; } - s3c_pm_resume_gpio(ourchip); + samsung_pm_resume_gpio(ourchip); gpio_nr += ourchip->chip.ngpio; gpio_nr += CONFIG_S3C_GPIO_SPACE; diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index ae6f99834cdd..64ab65f0fdbc 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -268,8 +268,8 @@ static int s3c_pm_enter(suspend_state_t state) /* save all necessary core registers not covered by the drivers */ - s3c_pm_save_gpios(); - s3c_pm_saved_gpios(); + samsung_pm_save_gpios(); + samsung_pm_saved_gpios(); s3c_pm_save_uarts(); s3c_pm_save_core(); @@ -306,7 +306,7 @@ static int s3c_pm_enter(suspend_state_t state) s3c_pm_restore_core(); s3c_pm_restore_uarts(); - s3c_pm_restore_gpios(); + samsung_pm_restore_gpios(); s3c_pm_restored_gpios(); s3c_pm_debug_init(); diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c index f1bba88ed2f5..a35ff3bcffe4 100644 --- a/arch/arm/plat-samsung/pwm-clock.c +++ b/arch/arm/plat-samsung/pwm-clock.c @@ -27,7 +27,7 @@ #include <plat/cpu.h> #include <plat/regs-timer.h> -#include <mach/pwm-clock.h> +#include <plat/pwm-clock.h> /* Each of the timers 0 through 5 go through the following * clock tree, with the inputs depending on the timers. @@ -339,8 +339,17 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) unsigned long bits; unsigned long shift = S3C2410_TCFG1_SHIFT(id); + unsigned long mux_tclk; + + if (soc_is_s3c24xx()) + mux_tclk = S3C2410_TCFG1_MUX_TCLK; + else if (soc_is_s5p6440() || soc_is_s5p6450()) + mux_tclk = 0; + else + mux_tclk = S3C64XX_TCFG1_MUX_TCLK; + if (parent == s3c24xx_pwmclk_tclk(id)) - bits = S3C_TCFG1_MUX_TCLK << shift; + bits = mux_tclk << shift; else if (parent == s3c24xx_pwmclk_tdiv(id)) bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; else diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 8b3c745b1b05..74603ca06e34 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -95,10 +95,6 @@ config GPIO_EP93XX depends on ARCH_EP93XX select GPIO_GENERIC -config GPIO_EXYNOS4 - def_bool y - depends on CPU_EXYNOS4210 - config GPIO_MPC5200 def_bool y depends on PPC_MPC52xx @@ -131,18 +127,6 @@ config GPIO_MXS select GPIO_GENERIC select GENERIC_IRQ_CHIP -config GPIO_PLAT_SAMSUNG - def_bool y - depends on SAMSUNG_GPIOLIB_4BIT - -config GPIO_S5PC100 - def_bool y - depends on CPU_S5PC100 - -config GPIO_S5PV210 - def_bool y - depends on CPU_S5PV210 - config GPIO_PL061 bool "PrimeCell PL061 GPIO support" depends on ARM_AMBA diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 19c5d27b6d2e..4a9ad2f99ada 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -16,7 +16,6 @@ obj-$(CONFIG_GPIO_CS5535) += gpio-cs5535.o obj-$(CONFIG_GPIO_DA9052) += gpio-da9052.o obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o -obj-$(CONFIG_GPIO_EXYNOS4) += gpio-exynos4.o obj-$(CONFIG_GPIO_IT8761E) += gpio-it8761e.o obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o obj-$(CONFIG_MACH_KS8695) += gpio-ks8695.o @@ -42,10 +41,7 @@ obj-$(CONFIG_GPIO_PCH) += gpio-pch.o obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o obj-$(CONFIG_PLAT_PXA) += gpio-pxa.o obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o - -obj-$(CONFIG_GPIO_PLAT_SAMSUNG) += gpio-plat-samsung.o -obj-$(CONFIG_GPIO_S5PC100) += gpio-s5pc100.o -obj-$(CONFIG_GPIO_S5PV210) += gpio-s5pv210.o +obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o obj-$(CONFIG_GPIO_SCH) += gpio-sch.o obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o diff --git a/drivers/gpio/gpio-exynos4.c b/drivers/gpio/gpio-exynos4.c deleted file mode 100644 index d24b337cf1ac..000000000000 --- a/drivers/gpio/gpio-exynos4.c +++ /dev/null @@ -1,385 +0,0 @@ -/* - * EXYNOS4 - GPIOlib support - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/gpio.h> - -#include <mach/map.h> - -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> - -int s3c_gpio_setpull_exynos4(struct s3c_gpio_chip *chip, - unsigned int off, s3c_gpio_pull_t pull) -{ - if (pull == S3C_GPIO_PULL_UP) - pull = 3; - - return s3c_gpio_setpull_updown(chip, off, pull); -} - -s3c_gpio_pull_t s3c_gpio_getpull_exynos4(struct s3c_gpio_chip *chip, - unsigned int off) -{ - s3c_gpio_pull_t pull; - - pull = s3c_gpio_getpull_updown(chip, off); - if (pull == 3) - pull = S3C_GPIO_PULL_UP; - - return pull; -} - -static struct s3c_gpio_cfg gpio_cfg = { - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_exynos4, - .get_pull = s3c_gpio_getpull_exynos4, -}; - -static struct s3c_gpio_cfg gpio_cfg_noint = { - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_exynos4, - .get_pull = s3c_gpio_getpull_exynos4, -}; - -/* - * Following are the gpio banks in v310. - * - * The 'config' member when left to NULL, is initialized to the default - * structure gpio_cfg in the init function below. - * - * The 'base' member is also initialized in the init function below. - * Note: The initialization of 'base' member of s3c_gpio_chip structure - * uses the above macro and depends on the banks being listed in order here. - */ -static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = { - { - .chip = { - .base = EXYNOS4_GPA0(0), - .ngpio = EXYNOS4_GPIO_A0_NR, - .label = "GPA0", - }, - }, { - .chip = { - .base = EXYNOS4_GPA1(0), - .ngpio = EXYNOS4_GPIO_A1_NR, - .label = "GPA1", - }, - }, { - .chip = { - .base = EXYNOS4_GPB(0), - .ngpio = EXYNOS4_GPIO_B_NR, - .label = "GPB", - }, - }, { - .chip = { - .base = EXYNOS4_GPC0(0), - .ngpio = EXYNOS4_GPIO_C0_NR, - .label = "GPC0", - }, - }, { - .chip = { - .base = EXYNOS4_GPC1(0), - .ngpio = EXYNOS4_GPIO_C1_NR, - .label = "GPC1", - }, - }, { - .chip = { - .base = EXYNOS4_GPD0(0), - .ngpio = EXYNOS4_GPIO_D0_NR, - .label = "GPD0", - }, - }, { - .chip = { - .base = EXYNOS4_GPD1(0), - .ngpio = EXYNOS4_GPIO_D1_NR, - .label = "GPD1", - }, - }, { - .chip = { - .base = EXYNOS4_GPE0(0), - .ngpio = EXYNOS4_GPIO_E0_NR, - .label = "GPE0", - }, - }, { - .chip = { - .base = EXYNOS4_GPE1(0), - .ngpio = EXYNOS4_GPIO_E1_NR, - .label = "GPE1", - }, - }, { - .chip = { - .base = EXYNOS4_GPE2(0), - .ngpio = EXYNOS4_GPIO_E2_NR, - .label = "GPE2", - }, - }, { - .chip = { - .base = EXYNOS4_GPE3(0), - .ngpio = EXYNOS4_GPIO_E3_NR, - .label = "GPE3", - }, - }, { - .chip = { - .base = EXYNOS4_GPE4(0), - .ngpio = EXYNOS4_GPIO_E4_NR, - .label = "GPE4", - }, - }, { - .chip = { - .base = EXYNOS4_GPF0(0), - .ngpio = EXYNOS4_GPIO_F0_NR, - .label = "GPF0", - }, - }, { - .chip = { - .base = EXYNOS4_GPF1(0), - .ngpio = EXYNOS4_GPIO_F1_NR, - .label = "GPF1", - }, - }, { - .chip = { - .base = EXYNOS4_GPF2(0), - .ngpio = EXYNOS4_GPIO_F2_NR, - .label = "GPF2", - }, - }, { - .chip = { - .base = EXYNOS4_GPF3(0), - .ngpio = EXYNOS4_GPIO_F3_NR, - .label = "GPF3", - }, - }, -}; - -static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = { - { - .chip = { - .base = EXYNOS4_GPJ0(0), - .ngpio = EXYNOS4_GPIO_J0_NR, - .label = "GPJ0", - }, - }, { - .chip = { - .base = EXYNOS4_GPJ1(0), - .ngpio = EXYNOS4_GPIO_J1_NR, - .label = "GPJ1", - }, - }, { - .chip = { - .base = EXYNOS4_GPK0(0), - .ngpio = EXYNOS4_GPIO_K0_NR, - .label = "GPK0", - }, - }, { - .chip = { - .base = EXYNOS4_GPK1(0), - .ngpio = EXYNOS4_GPIO_K1_NR, - .label = "GPK1", - }, - }, { - .chip = { - .base = EXYNOS4_GPK2(0), - .ngpio = EXYNOS4_GPIO_K2_NR, - .label = "GPK2", - }, - }, { - .chip = { - .base = EXYNOS4_GPK3(0), - .ngpio = EXYNOS4_GPIO_K3_NR, - .label = "GPK3", - }, - }, { - .chip = { - .base = EXYNOS4_GPL0(0), - .ngpio = EXYNOS4_GPIO_L0_NR, - .label = "GPL0", - }, - }, { - .chip = { - .base = EXYNOS4_GPL1(0), - .ngpio = EXYNOS4_GPIO_L1_NR, - .label = "GPL1", - }, - }, { - .chip = { - .base = EXYNOS4_GPL2(0), - .ngpio = EXYNOS4_GPIO_L2_NR, - .label = "GPL2", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = EXYNOS4_GPY0(0), - .ngpio = EXYNOS4_GPIO_Y0_NR, - .label = "GPY0", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = EXYNOS4_GPY1(0), - .ngpio = EXYNOS4_GPIO_Y1_NR, - .label = "GPY1", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = EXYNOS4_GPY2(0), - .ngpio = EXYNOS4_GPIO_Y2_NR, - .label = "GPY2", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = EXYNOS4_GPY3(0), - .ngpio = EXYNOS4_GPIO_Y3_NR, - .label = "GPY3", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = EXYNOS4_GPY4(0), - .ngpio = EXYNOS4_GPIO_Y4_NR, - .label = "GPY4", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = EXYNOS4_GPY5(0), - .ngpio = EXYNOS4_GPIO_Y5_NR, - .label = "GPY5", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = EXYNOS4_GPY6(0), - .ngpio = EXYNOS4_GPIO_Y6_NR, - .label = "GPY6", - }, - }, { - .base = (S5P_VA_GPIO2 + 0xC00), - .config = &gpio_cfg_noint, - .irq_base = IRQ_EINT(0), - .chip = { - .base = EXYNOS4_GPX0(0), - .ngpio = EXYNOS4_GPIO_X0_NR, - .label = "GPX0", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = (S5P_VA_GPIO2 + 0xC20), - .config = &gpio_cfg_noint, - .irq_base = IRQ_EINT(8), - .chip = { - .base = EXYNOS4_GPX1(0), - .ngpio = EXYNOS4_GPIO_X1_NR, - .label = "GPX1", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = (S5P_VA_GPIO2 + 0xC40), - .config = &gpio_cfg_noint, - .irq_base = IRQ_EINT(16), - .chip = { - .base = EXYNOS4_GPX2(0), - .ngpio = EXYNOS4_GPIO_X2_NR, - .label = "GPX2", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = (S5P_VA_GPIO2 + 0xC60), - .config = &gpio_cfg_noint, - .irq_base = IRQ_EINT(24), - .chip = { - .base = EXYNOS4_GPX3(0), - .ngpio = EXYNOS4_GPIO_X3_NR, - .label = "GPX3", - .to_irq = samsung_gpiolib_to_irq, - }, - }, -}; - -static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = { - { - .chip = { - .base = EXYNOS4_GPZ(0), - .ngpio = EXYNOS4_GPIO_Z_NR, - .label = "GPZ", - }, - }, -}; - -static __init int exynos4_gpiolib_init(void) -{ - struct s3c_gpio_chip *chip; - int i; - int group = 0; - int nr_chips; - - /* GPIO part 1 */ - - chip = exynos4_gpio_part1_4bit; - nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit); - - for (i = 0; i < nr_chips; i++, chip++) { - if (chip->config == NULL) { - chip->config = &gpio_cfg; - /* Assign the GPIO interrupt group */ - chip->group = group++; - } - if (chip->base == NULL) - chip->base = S5P_VA_GPIO1 + (i) * 0x20; - } - - samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips); - - /* GPIO part 2 */ - - chip = exynos4_gpio_part2_4bit; - nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit); - - for (i = 0; i < nr_chips; i++, chip++) { - if (chip->config == NULL) { - chip->config = &gpio_cfg; - /* Assign the GPIO interrupt group */ - chip->group = group++; - } - if (chip->base == NULL) - chip->base = S5P_VA_GPIO2 + (i) * 0x20; - } - - samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips); - - /* GPIO part 3 */ - - chip = exynos4_gpio_part3_4bit; - nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit); - - for (i = 0; i < nr_chips; i++, chip++) { - if (chip->config == NULL) { - chip->config = &gpio_cfg; - /* Assign the GPIO interrupt group */ - chip->group = group++; - } - if (chip->base == NULL) - chip->base = S5P_VA_GPIO3 + (i) * 0x20; - } - - samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips); - s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS); - s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS); - - return 0; -} -core_initcall(exynos4_gpiolib_init); diff --git a/drivers/gpio/gpio-plat-samsung.c b/drivers/gpio/gpio-plat-samsung.c deleted file mode 100644 index ef67f1952a72..000000000000 --- a/drivers/gpio/gpio-plat-samsung.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * Copyright (c) 2009 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * SAMSUNG - GPIOlib support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> - -#ifndef DEBUG_GPIO -#define gpio_dbg(x...) do { } while (0) -#else -#define gpio_dbg(x...) printk(KERN_DEBUG x) -#endif - -/* The samsung_gpiolib_4bit routines are to control the gpio banks where - * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the - * following example: - * - * base + 0x00: Control register, 4 bits per gpio - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Data register, 1 bit per gpio - * bit n: data bit n - * - * Note, since the data register is one bit per gpio and is at base + 0x4 - * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of - * the output. -*/ - -static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - - con = __raw_readl(base + GPIOCON_OFF); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, base + GPIOCON_OFF); - - gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); - - return 0; -} - -static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - unsigned long dat; - - con = __raw_readl(base + GPIOCON_OFF); - con &= ~(0xf << con_4bit_shift(offset)); - con |= 0x1 << con_4bit_shift(offset); - - dat = __raw_readl(base + GPIODAT_OFF); - - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + GPIODAT_OFF); - __raw_writel(con, base + GPIOCON_OFF); - __raw_writel(dat, base + GPIODAT_OFF); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - -/* The next set of routines are for the case where the GPIO configuration - * registers are 4 bits per GPIO but there is more than one register (the - * bank has more than 8 GPIOs. - * - * This case is the similar to the 4 bit case, but the registers are as - * follows: - * - * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x08: Data register, 1 bit per gpio - * bit n: data bit n - * - * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we - * store the 'base + 0x4' address so that these routines see the data - * register at ourchip->base + 0x04. - */ - -static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - - if (offset > 7) - offset -= 8; - else - regcon -= 4; - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, regcon); - - gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); - - return 0; -} - -static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - unsigned long dat; - unsigned con_offset = offset; - - if (con_offset > 7) - con_offset -= 8; - else - regcon -= 4; - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(con_offset)); - con |= 0x1 << con_4bit_shift(con_offset); - - dat = __raw_readl(base + GPIODAT_OFF); - - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + GPIODAT_OFF); - __raw_writel(con, regcon); - __raw_writel(dat, base + GPIODAT_OFF); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - -void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip) -{ - chip->chip.direction_input = samsung_gpiolib_4bit_input; - chip->chip.direction_output = samsung_gpiolib_4bit_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - -void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) -{ - chip->chip.direction_input = samsung_gpiolib_4bit2_input; - chip->chip.direction_output = samsung_gpiolib_4bit2_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - -void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, - int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chip++) { - samsung_gpiolib_add_4bit(chip); - s3c_gpiolib_add(chip); - } -} - -void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, - int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chip++) { - samsung_gpiolib_add_4bit2(chip); - s3c_gpiolib_add(chip); - } -} - -void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, - int nr_chips) -{ - for (; nr_chips > 0; nr_chips--, chip++) - s3c_gpiolib_add(chip); -} diff --git a/drivers/gpio/gpio-s5pc100.c b/drivers/gpio/gpio-s5pc100.c deleted file mode 100644 index 7f87b0c76e0b..000000000000 --- a/drivers/gpio/gpio-s5pc100.c +++ /dev/null @@ -1,354 +0,0 @@ -/* - * S5PC100 - GPIOlib support - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Copyright 2009 Samsung Electronics Co - * Kyungmin Park <kyungmin.park@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/gpio.h> - -#include <mach/map.h> -#include <mach/regs-gpio.h> - -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> - -/* S5PC100 GPIO bank summary: - * - * Bank GPIOs Style INT Type - * A0 8 4Bit GPIO_INT0 - * A1 5 4Bit GPIO_INT1 - * B 8 4Bit GPIO_INT2 - * C 5 4Bit GPIO_INT3 - * D 7 4Bit GPIO_INT4 - * E0 8 4Bit GPIO_INT5 - * E1 6 4Bit GPIO_INT6 - * F0 8 4Bit GPIO_INT7 - * F1 8 4Bit GPIO_INT8 - * F2 8 4Bit GPIO_INT9 - * F3 4 4Bit GPIO_INT10 - * G0 8 4Bit GPIO_INT11 - * G1 3 4Bit GPIO_INT12 - * G2 7 4Bit GPIO_INT13 - * G3 7 4Bit GPIO_INT14 - * H0 8 4Bit WKUP_INT - * H1 8 4Bit WKUP_INT - * H2 8 4Bit WKUP_INT - * H3 8 4Bit WKUP_INT - * I 8 4Bit GPIO_INT15 - * J0 8 4Bit GPIO_INT16 - * J1 5 4Bit GPIO_INT17 - * J2 8 4Bit GPIO_INT18 - * J3 8 4Bit GPIO_INT19 - * J4 4 4Bit GPIO_INT20 - * K0 8 4Bit None - * K1 6 4Bit None - * K2 8 4Bit None - * K3 8 4Bit None - * L0 8 4Bit None - * L1 8 4Bit None - * L2 8 4Bit None - * L3 8 4Bit None - */ - -static struct s3c_gpio_cfg gpio_cfg = { - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -static struct s3c_gpio_cfg gpio_cfg_eint = { - .cfg_eint = 0xf, - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -static struct s3c_gpio_cfg gpio_cfg_noint = { - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -/* - * GPIO bank's base address given the index of the bank in the - * list of all gpio banks. - */ -#define S5PC100_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) - -/* - * Following are the gpio banks in S5PC100. - * - * The 'config' member when left to NULL, is initialized to the default - * structure gpio_cfg in the init function below. - * - * The 'base' member is also initialized in the init function below. - * Note: The initialization of 'base' member of s3c_gpio_chip structure - * uses the above macro and depends on the banks being listed in order here. - */ -static struct s3c_gpio_chip s5pc100_gpio_chips[] = { - { - .chip = { - .base = S5PC100_GPA0(0), - .ngpio = S5PC100_GPIO_A0_NR, - .label = "GPA0", - }, - }, { - .chip = { - .base = S5PC100_GPA1(0), - .ngpio = S5PC100_GPIO_A1_NR, - .label = "GPA1", - }, - }, { - .chip = { - .base = S5PC100_GPB(0), - .ngpio = S5PC100_GPIO_B_NR, - .label = "GPB", - }, - }, { - .chip = { - .base = S5PC100_GPC(0), - .ngpio = S5PC100_GPIO_C_NR, - .label = "GPC", - }, - }, { - .chip = { - .base = S5PC100_GPD(0), - .ngpio = S5PC100_GPIO_D_NR, - .label = "GPD", - }, - }, { - .chip = { - .base = S5PC100_GPE0(0), - .ngpio = S5PC100_GPIO_E0_NR, - .label = "GPE0", - }, - }, { - .chip = { - .base = S5PC100_GPE1(0), - .ngpio = S5PC100_GPIO_E1_NR, - .label = "GPE1", - }, - }, { - .chip = { - .base = S5PC100_GPF0(0), - .ngpio = S5PC100_GPIO_F0_NR, - .label = "GPF0", - }, - }, { - .chip = { - .base = S5PC100_GPF1(0), - .ngpio = S5PC100_GPIO_F1_NR, - .label = "GPF1", - }, - }, { - .chip = { - .base = S5PC100_GPF2(0), - .ngpio = S5PC100_GPIO_F2_NR, - .label = "GPF2", - }, - }, { - .chip = { - .base = S5PC100_GPF3(0), - .ngpio = S5PC100_GPIO_F3_NR, - .label = "GPF3", - }, - }, { - .chip = { - .base = S5PC100_GPG0(0), - .ngpio = S5PC100_GPIO_G0_NR, - .label = "GPG0", - }, - }, { - .chip = { - .base = S5PC100_GPG1(0), - .ngpio = S5PC100_GPIO_G1_NR, - .label = "GPG1", - }, - }, { - .chip = { - .base = S5PC100_GPG2(0), - .ngpio = S5PC100_GPIO_G2_NR, - .label = "GPG2", - }, - }, { - .chip = { - .base = S5PC100_GPG3(0), - .ngpio = S5PC100_GPIO_G3_NR, - .label = "GPG3", - }, - }, { - .chip = { - .base = S5PC100_GPI(0), - .ngpio = S5PC100_GPIO_I_NR, - .label = "GPI", - }, - }, { - .chip = { - .base = S5PC100_GPJ0(0), - .ngpio = S5PC100_GPIO_J0_NR, - .label = "GPJ0", - }, - }, { - .chip = { - .base = S5PC100_GPJ1(0), - .ngpio = S5PC100_GPIO_J1_NR, - .label = "GPJ1", - }, - }, { - .chip = { - .base = S5PC100_GPJ2(0), - .ngpio = S5PC100_GPIO_J2_NR, - .label = "GPJ2", - }, - }, { - .chip = { - .base = S5PC100_GPJ3(0), - .ngpio = S5PC100_GPIO_J3_NR, - .label = "GPJ3", - }, - }, { - .chip = { - .base = S5PC100_GPJ4(0), - .ngpio = S5PC100_GPIO_J4_NR, - .label = "GPJ4", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PC100_GPK0(0), - .ngpio = S5PC100_GPIO_K0_NR, - .label = "GPK0", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PC100_GPK1(0), - .ngpio = S5PC100_GPIO_K1_NR, - .label = "GPK1", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PC100_GPK2(0), - .ngpio = S5PC100_GPIO_K2_NR, - .label = "GPK2", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PC100_GPK3(0), - .ngpio = S5PC100_GPIO_K3_NR, - .label = "GPK3", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PC100_GPL0(0), - .ngpio = S5PC100_GPIO_L0_NR, - .label = "GPL0", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PC100_GPL1(0), - .ngpio = S5PC100_GPIO_L1_NR, - .label = "GPL1", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PC100_GPL2(0), - .ngpio = S5PC100_GPIO_L2_NR, - .label = "GPL2", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PC100_GPL3(0), - .ngpio = S5PC100_GPIO_L3_NR, - .label = "GPL3", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PC100_GPL4(0), - .ngpio = S5PC100_GPIO_L4_NR, - .label = "GPL4", - }, - }, { - .base = (S5P_VA_GPIO + 0xC00), - .config = &gpio_cfg_eint, - .irq_base = IRQ_EINT(0), - .chip = { - .base = S5PC100_GPH0(0), - .ngpio = S5PC100_GPIO_H0_NR, - .label = "GPH0", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = (S5P_VA_GPIO + 0xC20), - .config = &gpio_cfg_eint, - .irq_base = IRQ_EINT(8), - .chip = { - .base = S5PC100_GPH1(0), - .ngpio = S5PC100_GPIO_H1_NR, - .label = "GPH1", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = (S5P_VA_GPIO + 0xC40), - .config = &gpio_cfg_eint, - .irq_base = IRQ_EINT(16), - .chip = { - .base = S5PC100_GPH2(0), - .ngpio = S5PC100_GPIO_H2_NR, - .label = "GPH2", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = (S5P_VA_GPIO + 0xC60), - .config = &gpio_cfg_eint, - .irq_base = IRQ_EINT(24), - .chip = { - .base = S5PC100_GPH3(0), - .ngpio = S5PC100_GPIO_H3_NR, - .label = "GPH3", - .to_irq = samsung_gpiolib_to_irq, - }, - }, -}; - -static __init int s5pc100_gpiolib_init(void) -{ - struct s3c_gpio_chip *chip = s5pc100_gpio_chips; - int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); - int gpioint_group = 0; - int i; - - for (i = 0; i < nr_chips; i++, chip++) { - if (chip->config == NULL) { - chip->config = &gpio_cfg; - chip->group = gpioint_group++; - } - if (chip->base == NULL) - chip->base = S5PC100_BANK_BASE(i); - } - - samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips); - s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); - - return 0; -} -core_initcall(s5pc100_gpiolib_init); diff --git a/drivers/gpio/gpio-s5pv210.c b/drivers/gpio/gpio-s5pv210.c deleted file mode 100644 index eb12f1602de9..000000000000 --- a/drivers/gpio/gpio-s5pv210.c +++ /dev/null @@ -1,287 +0,0 @@ -/* - * S5PV210 - GPIOlib support - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> -#include <mach/map.h> - -static struct s3c_gpio_cfg gpio_cfg = { - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -static struct s3c_gpio_cfg gpio_cfg_noint = { - .set_config = s3c_gpio_setcfg_s3c64xx_4bit, - .set_pull = s3c_gpio_setpull_updown, - .get_pull = s3c_gpio_getpull_updown, -}; - -/* GPIO bank's base address given the index of the bank in the - * list of all gpio banks. - */ -#define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) - -/* - * Following are the gpio banks in v210. - * - * The 'config' member when left to NULL, is initialized to the default - * structure gpio_cfg in the init function below. - * - * The 'base' member is also initialized in the init function below. - * Note: The initialization of 'base' member of s3c_gpio_chip structure - * uses the above macro and depends on the banks being listed in order here. - */ -static struct s3c_gpio_chip s5pv210_gpio_4bit[] = { - { - .chip = { - .base = S5PV210_GPA0(0), - .ngpio = S5PV210_GPIO_A0_NR, - .label = "GPA0", - }, - }, { - .chip = { - .base = S5PV210_GPA1(0), - .ngpio = S5PV210_GPIO_A1_NR, - .label = "GPA1", - }, - }, { - .chip = { - .base = S5PV210_GPB(0), - .ngpio = S5PV210_GPIO_B_NR, - .label = "GPB", - }, - }, { - .chip = { - .base = S5PV210_GPC0(0), - .ngpio = S5PV210_GPIO_C0_NR, - .label = "GPC0", - }, - }, { - .chip = { - .base = S5PV210_GPC1(0), - .ngpio = S5PV210_GPIO_C1_NR, - .label = "GPC1", - }, - }, { - .chip = { - .base = S5PV210_GPD0(0), - .ngpio = S5PV210_GPIO_D0_NR, - .label = "GPD0", - }, - }, { - .chip = { - .base = S5PV210_GPD1(0), - .ngpio = S5PV210_GPIO_D1_NR, - .label = "GPD1", - }, - }, { - .chip = { - .base = S5PV210_GPE0(0), - .ngpio = S5PV210_GPIO_E0_NR, - .label = "GPE0", - }, - }, { - .chip = { - .base = S5PV210_GPE1(0), - .ngpio = S5PV210_GPIO_E1_NR, - .label = "GPE1", - }, - }, { - .chip = { - .base = S5PV210_GPF0(0), - .ngpio = S5PV210_GPIO_F0_NR, - .label = "GPF0", - }, - }, { - .chip = { - .base = S5PV210_GPF1(0), - .ngpio = S5PV210_GPIO_F1_NR, - .label = "GPF1", - }, - }, { - .chip = { - .base = S5PV210_GPF2(0), - .ngpio = S5PV210_GPIO_F2_NR, - .label = "GPF2", - }, - }, { - .chip = { - .base = S5PV210_GPF3(0), - .ngpio = S5PV210_GPIO_F3_NR, - .label = "GPF3", - }, - }, { - .chip = { - .base = S5PV210_GPG0(0), - .ngpio = S5PV210_GPIO_G0_NR, - .label = "GPG0", - }, - }, { - .chip = { - .base = S5PV210_GPG1(0), - .ngpio = S5PV210_GPIO_G1_NR, - .label = "GPG1", - }, - }, { - .chip = { - .base = S5PV210_GPG2(0), - .ngpio = S5PV210_GPIO_G2_NR, - .label = "GPG2", - }, - }, { - .chip = { - .base = S5PV210_GPG3(0), - .ngpio = S5PV210_GPIO_G3_NR, - .label = "GPG3", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_GPI(0), - .ngpio = S5PV210_GPIO_I_NR, - .label = "GPI", - }, - }, { - .chip = { - .base = S5PV210_GPJ0(0), - .ngpio = S5PV210_GPIO_J0_NR, - .label = "GPJ0", - }, - }, { - .chip = { - .base = S5PV210_GPJ1(0), - .ngpio = S5PV210_GPIO_J1_NR, - .label = "GPJ1", - }, - }, { - .chip = { - .base = S5PV210_GPJ2(0), - .ngpio = S5PV210_GPIO_J2_NR, - .label = "GPJ2", - }, - }, { - .chip = { - .base = S5PV210_GPJ3(0), - .ngpio = S5PV210_GPIO_J3_NR, - .label = "GPJ3", - }, - }, { - .chip = { - .base = S5PV210_GPJ4(0), - .ngpio = S5PV210_GPIO_J4_NR, - .label = "GPJ4", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_MP01(0), - .ngpio = S5PV210_GPIO_MP01_NR, - .label = "MP01", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_MP02(0), - .ngpio = S5PV210_GPIO_MP02_NR, - .label = "MP02", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_MP03(0), - .ngpio = S5PV210_GPIO_MP03_NR, - .label = "MP03", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_MP04(0), - .ngpio = S5PV210_GPIO_MP04_NR, - .label = "MP04", - }, - }, { - .config = &gpio_cfg_noint, - .chip = { - .base = S5PV210_MP05(0), - .ngpio = S5PV210_GPIO_MP05_NR, - .label = "MP05", - }, - }, { - .base = (S5P_VA_GPIO + 0xC00), - .config = &gpio_cfg_noint, - .irq_base = IRQ_EINT(0), - .chip = { - .base = S5PV210_GPH0(0), - .ngpio = S5PV210_GPIO_H0_NR, - .label = "GPH0", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = (S5P_VA_GPIO + 0xC20), - .config = &gpio_cfg_noint, - .irq_base = IRQ_EINT(8), - .chip = { - .base = S5PV210_GPH1(0), - .ngpio = S5PV210_GPIO_H1_NR, - .label = "GPH1", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = (S5P_VA_GPIO + 0xC40), - .config = &gpio_cfg_noint, - .irq_base = IRQ_EINT(16), - .chip = { - .base = S5PV210_GPH2(0), - .ngpio = S5PV210_GPIO_H2_NR, - .label = "GPH2", - .to_irq = samsung_gpiolib_to_irq, - }, - }, { - .base = (S5P_VA_GPIO + 0xC60), - .config = &gpio_cfg_noint, - .irq_base = IRQ_EINT(24), - .chip = { - .base = S5PV210_GPH3(0), - .ngpio = S5PV210_GPIO_H3_NR, - .label = "GPH3", - .to_irq = samsung_gpiolib_to_irq, - }, - }, -}; - -static __init int s5pv210_gpiolib_init(void) -{ - struct s3c_gpio_chip *chip = s5pv210_gpio_4bit; - int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit); - int gpioint_group = 0; - int i = 0; - - for (i = 0; i < nr_chips; i++, chip++) { - if (chip->config == NULL) { - chip->config = &gpio_cfg; - chip->group = gpioint_group++; - } - if (chip->base == NULL) - chip->base = S5PV210_BANK_BASE(i); - } - - samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips); - s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); - - return 0; -} -core_initcall(s5pv210_gpiolib_init); diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c new file mode 100644 index 000000000000..b6be77ae4973 --- /dev/null +++ b/drivers/gpio/gpio-samsung.c @@ -0,0 +1,2688 @@ +/* + * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * SAMSUNG - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/spinlock.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/sysdev.h> +#include <linux/ioport.h> + +#include <asm/irq.h> + +#include <mach/hardware.h> +#include <mach/map.h> +#include <mach/regs-clock.h> +#include <mach/regs-gpio.h> + +#include <plat/cpu.h> +#include <plat/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> +#include <plat/gpio-fns.h> +#include <plat/pm.h> + +#ifndef DEBUG_GPIO +#define gpio_dbg(x...) do { } while (0) +#else +#define gpio_dbg(x...) printk(KERN_DEBUG x) +#endif + +int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull) +{ + void __iomem *reg = chip->base + 0x08; + int shift = off * 2; + u32 pup; + + pup = __raw_readl(reg); + pup &= ~(3 << shift); + pup |= pull << shift; + __raw_writel(pup, reg); + + return 0; +} + +samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip, + unsigned int off) +{ + void __iomem *reg = chip->base + 0x08; + int shift = off * 2; + u32 pup = __raw_readl(reg); + + pup >>= shift; + pup &= 0x3; + + return (__force samsung_gpio_pull_t)pup; +} + +int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull) +{ + switch (pull) { + case S3C_GPIO_PULL_NONE: + pull = 0x01; + break; + case S3C_GPIO_PULL_UP: + pull = 0x00; + break; + case S3C_GPIO_PULL_DOWN: + pull = 0x02; + break; + } + return samsung_gpio_setpull_updown(chip, off, pull); +} + +samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip, + unsigned int off) +{ + samsung_gpio_pull_t pull; + + pull = samsung_gpio_getpull_updown(chip, off); + + switch (pull) { + case 0x00: + pull = S3C_GPIO_PULL_UP; + break; + case 0x01: + case 0x03: + pull = S3C_GPIO_PULL_NONE; + break; + case 0x02: + pull = S3C_GPIO_PULL_DOWN; + break; + } + + return pull; +} + +static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull, + samsung_gpio_pull_t updown) +{ + void __iomem *reg = chip->base + 0x08; + u32 pup = __raw_readl(reg); + + if (pull == updown) + pup &= ~(1 << off); + else if (pull == S3C_GPIO_PULL_NONE) + pup |= (1 << off); + else + return -EINVAL; + + __raw_writel(pup, reg); + return 0; +} + +static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip, + unsigned int off, + samsung_gpio_pull_t updown) +{ + void __iomem *reg = chip->base + 0x08; + u32 pup = __raw_readl(reg); + + pup &= (1 << off); + return pup ? S3C_GPIO_PULL_NONE : updown; +} + +samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip, + unsigned int off) +{ + return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP); +} + +int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull) +{ + return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP); +} + +samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip, + unsigned int off) +{ + return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN); +} + +int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull) +{ + return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN); +} + +static int exynos4_gpio_setpull(struct samsung_gpio_chip *chip, + unsigned int off, samsung_gpio_pull_t pull) +{ + if (pull == S3C_GPIO_PULL_UP) + pull = 3; + + return samsung_gpio_setpull_updown(chip, off, pull); +} + +static samsung_gpio_pull_t exynos4_gpio_getpull(struct samsung_gpio_chip *chip, + unsigned int off) +{ + samsung_gpio_pull_t pull; + + pull = samsung_gpio_getpull_updown(chip, off); + + if (pull == 3) + pull = S3C_GPIO_PULL_UP; + + return pull; +} + +/* + * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @cfg: The configuration value to set. + * + * This helper deal with the GPIO cases where the control register + * has two bits of configuration per gpio, which have the following + * functions: + * 00 = input + * 01 = output + * 1x = special function + */ + +static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip, + unsigned int off, unsigned int cfg) +{ + void __iomem *reg = chip->base; + unsigned int shift = off * 2; + u32 con; + + if (samsung_gpio_is_cfg_special(cfg)) { + cfg &= 0xf; + if (cfg > 3) + return -EINVAL; + + cfg <<= shift; + } + + con = __raw_readl(reg); + con &= ~(0x3 << shift); + con |= cfg; + __raw_writel(con, reg); + + return 0; +} + +/* + * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * + * The reverse of samsung_gpio_setcfg_2bit(). Will return a value whicg + * could be directly passed back to samsung_gpio_setcfg_2bit(), from the + * S3C_GPIO_SPECIAL() macro. + */ + +static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip, + unsigned int off) +{ + u32 con; + + con = __raw_readl(chip->base); + con >>= off * 2; + con &= 3; + + /* this conversion works for IN and OUT as well as special mode */ + return S3C_GPIO_SPECIAL(con); +} + +/* + * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @cfg: The configuration value to set. + * + * This helper deal with the GPIO cases where the control register has 4 bits + * of control per GPIO, generally in the form of: + * 0000 = Input + * 0001 = Output + * others = Special functions (dependent on bank) + * + * Note, since the code to deal with the case where there are two control + * registers instead of one, we do not have a separate set of functions for + * each case. + */ + +static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip, + unsigned int off, unsigned int cfg) +{ + void __iomem *reg = chip->base; + unsigned int shift = (off & 7) * 4; + u32 con; + + if (off < 8 && chip->chip.ngpio > 8) + reg -= 4; + + if (samsung_gpio_is_cfg_special(cfg)) { + cfg &= 0xf; + cfg <<= shift; + } + + con = __raw_readl(reg); + con &= ~(0xf << shift); + con |= cfg; + __raw_writel(con, reg); + + return 0; +} + +/* + * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read. + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * + * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration + * register setting into a value the software can use, such as could be passed + * to samsung_gpio_setcfg_4bit(). + * + * @sa samsung_gpio_getcfg_2bit + */ + +static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip, + unsigned int off) +{ + void __iomem *reg = chip->base; + unsigned int shift = (off & 7) * 4; + u32 con; + + if (off < 8 && chip->chip.ngpio > 8) + reg -= 4; + + con = __raw_readl(reg); + con >>= shift; + con &= 0xf; + + /* this conversion works for IN and OUT as well as special mode */ + return S3C_GPIO_SPECIAL(con); +} + +/* + * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A) + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * @cfg: The configuration value to set. + * + * This helper deal with the GPIO cases where the control register + * has one bit of configuration for the gpio, where setting the bit + * means the pin is in special function mode and unset means output. + */ + +static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip, + unsigned int off, unsigned int cfg) +{ + void __iomem *reg = chip->base; + unsigned int shift = off; + u32 con; + + if (samsung_gpio_is_cfg_special(cfg)) { + cfg &= 0xf; + + /* Map output to 0, and SFN2 to 1 */ + cfg -= 1; + if (cfg > 1) + return -EINVAL; + + cfg <<= shift; + } + + con = __raw_readl(reg); + con &= ~(0x1 << shift); + con |= cfg; + __raw_writel(con, reg); + + return 0; +} + +/* + * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A) + * @chip: The gpio chip that is being configured. + * @off: The offset for the GPIO being configured. + * + * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable + * GPIO configuration value. + * + * @sa samsung_gpio_getcfg_2bit + * @sa samsung_gpio_getcfg_4bit + */ + +static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip, + unsigned int off) +{ + u32 con; + + con = __raw_readl(chip->base); + con >>= off; + con &= 1; + con++; + + return S3C_GPIO_SFN(con); +} + +static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip, + unsigned int off, unsigned int cfg) +{ + void __iomem *reg = chip->base; + unsigned int shift; + u32 con; + + switch (off) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + shift = (off & 7) * 4; + reg -= 4; + break; + case 6: + shift = ((off + 1) & 7) * 4; + reg -= 4; + default: + shift = ((off + 1) & 7) * 4; + break; + } + + if (samsung_gpio_is_cfg_special(cfg)) { + cfg &= 0xf; + cfg <<= shift; + } + + con = __raw_readl(reg); + con &= ~(0xf << shift); + con |= cfg; + __raw_writel(con, reg); + + return 0; +} + +static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chipcfg++) { + if (!chipcfg->set_config) + chipcfg->set_config = samsung_gpio_setcfg_4bit; + if (!chipcfg->get_config) + chipcfg->get_config = samsung_gpio_getcfg_4bit; + if (!chipcfg->set_pull) + chipcfg->set_pull = samsung_gpio_setpull_updown; + if (!chipcfg->get_pull) + chipcfg->get_pull = samsung_gpio_getpull_updown; + } +} + +struct samsung_gpio_cfg s3c24xx_gpiocfg_default = { + .set_config = samsung_gpio_setcfg_2bit, + .get_config = samsung_gpio_getcfg_2bit, +}; + +static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = { + .set_config = s3c24xx_gpio_setcfg_abank, + .get_config = s3c24xx_gpio_getcfg_abank, +}; + +static struct samsung_gpio_cfg exynos4_gpio_cfg = { + .set_pull = exynos4_gpio_setpull, + .get_pull = exynos4_gpio_getpull, + .set_config = samsung_gpio_setcfg_4bit, + .get_config = samsung_gpio_getcfg_4bit, +}; + +static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = { + .cfg_eint = 0x3, + .set_config = s5p64x0_gpio_setcfg_rbank, + .get_config = samsung_gpio_getcfg_4bit, + .set_pull = samsung_gpio_setpull_updown, + .get_pull = samsung_gpio_getpull_updown, +}; + +static struct samsung_gpio_cfg samsung_gpio_cfgs[] = { + { + .cfg_eint = 0x0, + }, { + .cfg_eint = 0x3, + }, { + .cfg_eint = 0x7, + }, { + .cfg_eint = 0xF, + }, { + .cfg_eint = 0x0, + .set_config = samsung_gpio_setcfg_2bit, + .get_config = samsung_gpio_getcfg_2bit, + }, { + .cfg_eint = 0x2, + .set_config = samsung_gpio_setcfg_2bit, + .get_config = samsung_gpio_getcfg_2bit, + }, { + .cfg_eint = 0x3, + .set_config = samsung_gpio_setcfg_2bit, + .get_config = samsung_gpio_getcfg_2bit, + }, { + .set_config = samsung_gpio_setcfg_2bit, + .get_config = samsung_gpio_getcfg_2bit, + }, +}; + +/* + * Default routines for controlling GPIO, based on the original S3C24XX + * GPIO functions which deal with the case where each gpio bank of the + * chip is as following: + * + * base + 0x00: Control register, 2 bits per gpio + * gpio n: 2 bits starting at (2*n) + * 00 = input, 01 = output, others mean special-function + * base + 0x04: Data register, 1 bit per gpio + * bit n: data bit n +*/ + +static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long con; + + samsung_gpio_lock(ourchip, flags); + + con = __raw_readl(base + 0x00); + con &= ~(3 << (offset * 2)); + + __raw_writel(con, base + 0x00); + + samsung_gpio_unlock(ourchip, flags); + return 0; +} + +static int samsung_gpiolib_2bit_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long dat; + unsigned long con; + + samsung_gpio_lock(ourchip, flags); + + dat = __raw_readl(base + 0x04); + dat &= ~(1 << offset); + if (value) + dat |= 1 << offset; + __raw_writel(dat, base + 0x04); + + con = __raw_readl(base + 0x00); + con &= ~(3 << (offset * 2)); + con |= 1 << (offset * 2); + + __raw_writel(con, base + 0x00); + __raw_writel(dat, base + 0x04); + + samsung_gpio_unlock(ourchip, flags); + return 0; +} + +/* + * The samsung_gpiolib_4bit routines are to control the gpio banks where + * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the + * following example: + * + * base + 0x00: Control register, 4 bits per gpio + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Data register, 1 bit per gpio + * bit n: data bit n + * + * Note, since the data register is one bit per gpio and is at base + 0x4 + * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the + * state of the output. + */ + +static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + + con = __raw_readl(base + GPIOCON_OFF); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, base + GPIOCON_OFF); + + gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); + + return 0; +} + +static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + unsigned long dat; + + con = __raw_readl(base + GPIOCON_OFF); + con &= ~(0xf << con_4bit_shift(offset)); + con |= 0x1 << con_4bit_shift(offset); + + dat = __raw_readl(base + GPIODAT_OFF); + + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + GPIODAT_OFF); + __raw_writel(con, base + GPIOCON_OFF); + __raw_writel(dat, base + GPIODAT_OFF); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +/* + * The next set of routines are for the case where the GPIO configuration + * registers are 4 bits per GPIO but there is more than one register (the + * bank has more than 8 GPIOs. + * + * This case is the similar to the 4 bit case, but the registers are as + * follows: + * + * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x08: Data register, 1 bit per gpio + * bit n: data bit n + * + * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set + * routines we store the 'base + 0x4' address so that these routines see + * the data register at ourchip->base + 0x04. + */ + +static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + + if (offset > 7) + offset -= 8; + else + regcon -= 4; + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, regcon); + + gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); + + return 0; +} + +static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + unsigned long dat; + unsigned con_offset = offset; + + if (con_offset > 7) + con_offset -= 8; + else + regcon -= 4; + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(con_offset)); + con |= 0x1 << con_4bit_shift(con_offset); + + dat = __raw_readl(base + GPIODAT_OFF); + + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + GPIODAT_OFF); + __raw_writel(con, regcon); + __raw_writel(dat, base + GPIODAT_OFF); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +/* The next set of routines are for the case of s3c24xx bank a */ + +static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) +{ + return -EINVAL; +} + +static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long dat; + unsigned long con; + + local_irq_save(flags); + + con = __raw_readl(base + 0x00); + dat = __raw_readl(base + 0x04); + + dat &= ~(1 << offset); + if (value) + dat |= 1 << offset; + + __raw_writel(dat, base + 0x04); + + con &= ~(1 << offset); + + __raw_writel(con, base + 0x00); + __raw_writel(dat, base + 0x04); + + local_irq_restore(flags); + return 0; +} + +/* The next set of routines are for the case of s5p64x0 bank r */ + +static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + unsigned long flags; + + switch (offset) { + case 6: + offset += 1; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + regcon -= 4; + break; + default: + offset -= 7; + break; + } + + samsung_gpio_lock(ourchip, flags); + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, regcon); + + samsung_gpio_unlock(ourchip, flags); + + return 0; +} + +static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + unsigned long dat; + unsigned long flags; + unsigned con_offset = offset; + + switch (con_offset) { + case 6: + con_offset += 1; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + regcon -= 4; + break; + default: + con_offset -= 7; + break; + } + + samsung_gpio_lock(ourchip, flags); + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(con_offset)); + con |= 0x1 << con_4bit_shift(con_offset); + + dat = __raw_readl(base + GPIODAT_OFF); + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(con, regcon); + __raw_writel(dat, base + GPIODAT_OFF); + + samsung_gpio_unlock(ourchip, flags); + + return 0; +} + +static void samsung_gpiolib_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long flags; + unsigned long dat; + + samsung_gpio_lock(ourchip, flags); + + dat = __raw_readl(base + 0x04); + dat &= ~(1 << offset); + if (value) + dat |= 1 << offset; + __raw_writel(dat, base + 0x04); + + samsung_gpio_unlock(ourchip, flags); +} + +static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset) +{ + struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip); + unsigned long val; + + val = __raw_readl(ourchip->base + 0x04); + val >>= offset; + val &= 1; + + return val; +} + +/* + * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios + * for use with the configuration calls, and other parts of the s3c gpiolib + * support code. + * + * Not all s3c support code will need this, as some configurations of cpu + * may only support one or two different configuration options and have an + * easy gpio to samsung_gpio_chip mapping function. If this is the case, then + * the machine support file should provide its own samsung_gpiolib_getchip() + * and any other necessary functions. + */ + +#ifdef CONFIG_S3C_GPIO_TRACK +struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END]; + +static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip) +{ + unsigned int gpn; + int i; + + gpn = chip->chip.base; + for (i = 0; i < chip->chip.ngpio; i++, gpn++) { + BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios)); + s3c_gpios[gpn] = chip; + } +} +#endif /* CONFIG_S3C_GPIO_TRACK */ + +/* + * samsung_gpiolib_add() - add the Samsung gpio_chip. + * @chip: The chip to register + * + * This is a wrapper to gpiochip_add() that takes our specific gpio chip + * information and makes the necessary alterations for the platform and + * notes the information for use with the configuration systems and any + * other parts of the system. + */ + +static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip) +{ + struct gpio_chip *gc = &chip->chip; + int ret; + + BUG_ON(!chip->base); + BUG_ON(!gc->label); + BUG_ON(!gc->ngpio); + + spin_lock_init(&chip->lock); + + if (!gc->direction_input) + gc->direction_input = samsung_gpiolib_2bit_input; + if (!gc->direction_output) + gc->direction_output = samsung_gpiolib_2bit_output; + if (!gc->set) + gc->set = samsung_gpiolib_set; + if (!gc->get) + gc->get = samsung_gpiolib_get; + +#ifdef CONFIG_PM + if (chip->pm != NULL) { + if (!chip->pm->save || !chip->pm->resume) + printk(KERN_ERR "gpio: %s has missing PM functions\n", + gc->label); + } else + printk(KERN_ERR "gpio: %s has no PM function\n", gc->label); +#endif + + /* gpiochip_add() prints own failure message on error. */ + ret = gpiochip_add(gc); + if (ret >= 0) + s3c_gpiolib_track(chip); +} + +static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip, + int nr_chips, void __iomem *base) +{ + int i; + struct gpio_chip *gc = &chip->chip; + + for (i = 0 ; i < nr_chips; i++, chip++) { + if (!chip->config) + chip->config = &s3c24xx_gpiocfg_default; + if (!chip->pm) + chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); + if ((base != NULL) && (chip->base == NULL)) + chip->base = base + ((i) * 0x10); + + if (!gc->direction_input) + gc->direction_input = samsung_gpiolib_2bit_input; + if (!gc->direction_output) + gc->direction_output = samsung_gpiolib_2bit_output; + + samsung_gpiolib_add(chip); + } +} + +static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip, + int nr_chips, void __iomem *base, + unsigned int offset) +{ + int i; + + for (i = 0 ; i < nr_chips; i++, chip++) { + chip->chip.direction_input = samsung_gpiolib_2bit_input; + chip->chip.direction_output = samsung_gpiolib_2bit_output; + + if (!chip->config) + chip->config = &samsung_gpio_cfgs[7]; + if (!chip->pm) + chip->pm = __gpio_pm(&samsung_gpio_pm_2bit); + if ((base != NULL) && (chip->base == NULL)) + chip->base = base + ((i) * offset); + + samsung_gpiolib_add(chip); + } +} + +/* + * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config. + * @chip: The gpio chip that is being configured. + * @nr_chips: The no of chips (gpio ports) for the GPIO being configured. + * + * This helper deal with the GPIO cases where the control register has 4 bits + * of control per GPIO, generally in the form of: + * 0000 = Input + * 0001 = Output + * others = Special functions (dependent on bank) + * + * Note, since the code to deal with the case where there are two control + * registers instead of one, we do not have a separate set of function + * (samsung_gpiolib_add_4bit2_chips)for each case. + */ + +static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip, + int nr_chips, void __iomem *base) +{ + int i; + + for (i = 0 ; i < nr_chips; i++, chip++) { + chip->chip.direction_input = samsung_gpiolib_4bit_input; + chip->chip.direction_output = samsung_gpiolib_4bit_output; + + if (!chip->config) + chip->config = &samsung_gpio_cfgs[2]; + if (!chip->pm) + chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); + if ((base != NULL) && (chip->base == NULL)) + chip->base = base + ((i) * 0x20); + + samsung_gpiolib_add(chip); + } +} + +static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chip++) { + chip->chip.direction_input = samsung_gpiolib_4bit2_input; + chip->chip.direction_output = samsung_gpiolib_4bit2_output; + + if (!chip->config) + chip->config = &samsung_gpio_cfgs[2]; + if (!chip->pm) + chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); + + samsung_gpiolib_add(chip); + } +} + +static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chip++) { + chip->chip.direction_input = s5p64x0_gpiolib_rbank_input; + chip->chip.direction_output = s5p64x0_gpiolib_rbank_output; + + if (!chip->pm) + chip->pm = __gpio_pm(&samsung_gpio_pm_4bit); + + samsung_gpiolib_add(chip); + } +} + +int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip); + + return samsung_chip->irq_base + offset; +} + +#ifdef CONFIG_PLAT_S3C24XX +static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset) +{ + if (offset < 4) + return IRQ_EINT0 + offset; + + if (offset < 8) + return IRQ_EINT4 + offset - 4; + + return -EINVAL; +} +#endif + +#ifdef CONFIG_PLAT_S3C64XX +static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin) +{ + return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; +} + +static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin) +{ + return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; +} +#endif + +struct samsung_gpio_chip s3c24xx_gpios[] = { +#ifdef CONFIG_PLAT_S3C24XX + { + .config = &s3c24xx_gpiocfg_banka, + .chip = { + .base = S3C2410_GPA(0), + .owner = THIS_MODULE, + .label = "GPIOA", + .ngpio = 24, + .direction_input = s3c24xx_gpiolib_banka_input, + .direction_output = s3c24xx_gpiolib_banka_output, + }, + }, { + .chip = { + .base = S3C2410_GPB(0), + .owner = THIS_MODULE, + .label = "GPIOB", + .ngpio = 16, + }, + }, { + .chip = { + .base = S3C2410_GPC(0), + .owner = THIS_MODULE, + .label = "GPIOC", + .ngpio = 16, + }, + }, { + .chip = { + .base = S3C2410_GPD(0), + .owner = THIS_MODULE, + .label = "GPIOD", + .ngpio = 16, + }, + }, { + .chip = { + .base = S3C2410_GPE(0), + .label = "GPIOE", + .owner = THIS_MODULE, + .ngpio = 16, + }, + }, { + .chip = { + .base = S3C2410_GPF(0), + .owner = THIS_MODULE, + .label = "GPIOF", + .ngpio = 8, + .to_irq = s3c24xx_gpiolib_fbank_to_irq, + }, + }, { + .irq_base = IRQ_EINT8, + .chip = { + .base = S3C2410_GPG(0), + .owner = THIS_MODULE, + .label = "GPIOG", + .ngpio = 16, + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .chip = { + .base = S3C2410_GPH(0), + .owner = THIS_MODULE, + .label = "GPIOH", + .ngpio = 11, + }, + }, + /* GPIOS for the S3C2443 and later devices. */ + { + .base = S3C2440_GPJCON, + .chip = { + .base = S3C2410_GPJ(0), + .owner = THIS_MODULE, + .label = "GPIOJ", + .ngpio = 16, + }, + }, { + .base = S3C2443_GPKCON, + .chip = { + .base = S3C2410_GPK(0), + .owner = THIS_MODULE, + .label = "GPIOK", + .ngpio = 16, + }, + }, { + .base = S3C2443_GPLCON, + .chip = { + .base = S3C2410_GPL(0), + .owner = THIS_MODULE, + .label = "GPIOL", + .ngpio = 15, + }, + }, { + .base = S3C2443_GPMCON, + .chip = { + .base = S3C2410_GPM(0), + .owner = THIS_MODULE, + .label = "GPIOM", + .ngpio = 2, + }, + }, +#endif +}; + +/* + * GPIO bank summary: + * + * Bank GPIOs Style SlpCon ExtInt Group + * A 8 4Bit Yes 1 + * B 7 4Bit Yes 1 + * C 8 4Bit Yes 2 + * D 5 4Bit Yes 3 + * E 5 4Bit Yes None + * F 16 2Bit Yes 4 [1] + * G 7 4Bit Yes 5 + * H 10 4Bit[2] Yes 6 + * I 16 2Bit Yes None + * J 12 2Bit Yes None + * K 16 4Bit[2] No None + * L 15 4Bit[2] No None + * M 6 4Bit No IRQ_EINT + * N 16 2Bit No IRQ_EINT + * O 16 2Bit Yes 7 + * P 15 2Bit Yes 8 + * Q 9 2Bit Yes 9 + * + * [1] BANKF pins 14,15 do not form part of the external interrupt sources + * [2] BANK has two control registers, GPxCON0 and GPxCON1 + */ + +static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = { +#ifdef CONFIG_PLAT_S3C64XX + { + .chip = { + .base = S3C64XX_GPA(0), + .ngpio = S3C64XX_GPIO_A_NR, + .label = "GPA", + }, + }, { + .chip = { + .base = S3C64XX_GPB(0), + .ngpio = S3C64XX_GPIO_B_NR, + .label = "GPB", + }, + }, { + .chip = { + .base = S3C64XX_GPC(0), + .ngpio = S3C64XX_GPIO_C_NR, + .label = "GPC", + }, + }, { + .chip = { + .base = S3C64XX_GPD(0), + .ngpio = S3C64XX_GPIO_D_NR, + .label = "GPD", + }, + }, { + .config = &samsung_gpio_cfgs[0], + .chip = { + .base = S3C64XX_GPE(0), + .ngpio = S3C64XX_GPIO_E_NR, + .label = "GPE", + }, + }, { + .base = S3C64XX_GPG_BASE, + .chip = { + .base = S3C64XX_GPG(0), + .ngpio = S3C64XX_GPIO_G_NR, + .label = "GPG", + }, + }, { + .base = S3C64XX_GPM_BASE, + .config = &samsung_gpio_cfgs[1], + .chip = { + .base = S3C64XX_GPM(0), + .ngpio = S3C64XX_GPIO_M_NR, + .label = "GPM", + .to_irq = s3c64xx_gpiolib_mbank_to_irq, + }, + }, +#endif +}; + +static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = { +#ifdef CONFIG_PLAT_S3C64XX + { + .base = S3C64XX_GPH_BASE + 0x4, + .chip = { + .base = S3C64XX_GPH(0), + .ngpio = S3C64XX_GPIO_H_NR, + .label = "GPH", + }, + }, { + .base = S3C64XX_GPK_BASE + 0x4, + .config = &samsung_gpio_cfgs[0], + .chip = { + .base = S3C64XX_GPK(0), + .ngpio = S3C64XX_GPIO_K_NR, + .label = "GPK", + }, + }, { + .base = S3C64XX_GPL_BASE + 0x4, + .config = &samsung_gpio_cfgs[1], + .chip = { + .base = S3C64XX_GPL(0), + .ngpio = S3C64XX_GPIO_L_NR, + .label = "GPL", + .to_irq = s3c64xx_gpiolib_lbank_to_irq, + }, + }, +#endif +}; + +static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = { +#ifdef CONFIG_PLAT_S3C64XX + { + .base = S3C64XX_GPF_BASE, + .config = &samsung_gpio_cfgs[6], + .chip = { + .base = S3C64XX_GPF(0), + .ngpio = S3C64XX_GPIO_F_NR, + .label = "GPF", + }, + }, { + .config = &samsung_gpio_cfgs[7], + .chip = { + .base = S3C64XX_GPI(0), + .ngpio = S3C64XX_GPIO_I_NR, + .label = "GPI", + }, + }, { + .config = &samsung_gpio_cfgs[7], + .chip = { + .base = S3C64XX_GPJ(0), + .ngpio = S3C64XX_GPIO_J_NR, + .label = "GPJ", + }, + }, { + .config = &samsung_gpio_cfgs[6], + .chip = { + .base = S3C64XX_GPO(0), + .ngpio = S3C64XX_GPIO_O_NR, + .label = "GPO", + }, + }, { + .config = &samsung_gpio_cfgs[6], + .chip = { + .base = S3C64XX_GPP(0), + .ngpio = S3C64XX_GPIO_P_NR, + .label = "GPP", + }, + }, { + .config = &samsung_gpio_cfgs[6], + .chip = { + .base = S3C64XX_GPQ(0), + .ngpio = S3C64XX_GPIO_Q_NR, + .label = "GPQ", + }, + }, { + .base = S3C64XX_GPN_BASE, + .irq_base = IRQ_EINT(0), + .config = &samsung_gpio_cfgs[5], + .chip = { + .base = S3C64XX_GPN(0), + .ngpio = S3C64XX_GPIO_N_NR, + .label = "GPN", + .to_irq = samsung_gpiolib_to_irq, + }, + }, +#endif +}; + +/* + * S5P6440 GPIO bank summary: + * + * Bank GPIOs Style SlpCon ExtInt Group + * A 6 4Bit Yes 1 + * B 7 4Bit Yes 1 + * C 8 4Bit Yes 2 + * F 2 2Bit Yes 4 [1] + * G 7 4Bit Yes 5 + * H 10 4Bit[2] Yes 6 + * I 16 2Bit Yes None + * J 12 2Bit Yes None + * N 16 2Bit No IRQ_EINT + * P 8 2Bit Yes 8 + * R 15 4Bit[2] Yes 8 + */ + +static struct samsung_gpio_chip s5p6440_gpios_4bit[] = { +#ifdef CONFIG_CPU_S5P6440 + { + .chip = { + .base = S5P6440_GPA(0), + .ngpio = S5P6440_GPIO_A_NR, + .label = "GPA", + }, + }, { + .chip = { + .base = S5P6440_GPB(0), + .ngpio = S5P6440_GPIO_B_NR, + .label = "GPB", + }, + }, { + .chip = { + .base = S5P6440_GPC(0), + .ngpio = S5P6440_GPIO_C_NR, + .label = "GPC", + }, + }, { + .base = S5P64X0_GPG_BASE, + .chip = { + .base = S5P6440_GPG(0), + .ngpio = S5P6440_GPIO_G_NR, + .label = "GPG", + }, + }, +#endif +}; + +static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = { +#ifdef CONFIG_CPU_S5P6440 + { + .base = S5P64X0_GPH_BASE + 0x4, + .chip = { + .base = S5P6440_GPH(0), + .ngpio = S5P6440_GPIO_H_NR, + .label = "GPH", + }, + }, +#endif +}; + +static struct samsung_gpio_chip s5p6440_gpios_rbank[] = { +#ifdef CONFIG_CPU_S5P6440 + { + .base = S5P64X0_GPR_BASE + 0x4, + .config = &s5p64x0_gpio_cfg_rbank, + .chip = { + .base = S5P6440_GPR(0), + .ngpio = S5P6440_GPIO_R_NR, + .label = "GPR", + }, + }, +#endif +}; + +static struct samsung_gpio_chip s5p6440_gpios_2bit[] = { +#ifdef CONFIG_CPU_S5P6440 + { + .base = S5P64X0_GPF_BASE, + .config = &samsung_gpio_cfgs[6], + .chip = { + .base = S5P6440_GPF(0), + .ngpio = S5P6440_GPIO_F_NR, + .label = "GPF", + }, + }, { + .base = S5P64X0_GPI_BASE, + .config = &samsung_gpio_cfgs[4], + .chip = { + .base = S5P6440_GPI(0), + .ngpio = S5P6440_GPIO_I_NR, + .label = "GPI", + }, + }, { + .base = S5P64X0_GPJ_BASE, + .config = &samsung_gpio_cfgs[4], + .chip = { + .base = S5P6440_GPJ(0), + .ngpio = S5P6440_GPIO_J_NR, + .label = "GPJ", + }, + }, { + .base = S5P64X0_GPN_BASE, + .config = &samsung_gpio_cfgs[5], + .chip = { + .base = S5P6440_GPN(0), + .ngpio = S5P6440_GPIO_N_NR, + .label = "GPN", + }, + }, { + .base = S5P64X0_GPP_BASE, + .config = &samsung_gpio_cfgs[6], + .chip = { + .base = S5P6440_GPP(0), + .ngpio = S5P6440_GPIO_P_NR, + .label = "GPP", + }, + }, +#endif +}; + +/* + * S5P6450 GPIO bank summary: + * + * Bank GPIOs Style SlpCon ExtInt Group + * A 6 4Bit Yes 1 + * B 7 4Bit Yes 1 + * C 8 4Bit Yes 2 + * D 8 4Bit Yes None + * F 2 2Bit Yes None + * G 14 4Bit[2] Yes 5 + * H 10 4Bit[2] Yes 6 + * I 16 2Bit Yes None + * J 12 2Bit Yes None + * K 5 4Bit Yes None + * N 16 2Bit No IRQ_EINT + * P 11 2Bit Yes 8 + * Q 14 2Bit Yes None + * R 15 4Bit[2] Yes None + * S 8 2Bit Yes None + * + * [1] BANKF pins 14,15 do not form part of the external interrupt sources + * [2] BANK has two control registers, GPxCON0 and GPxCON1 + */ + +static struct samsung_gpio_chip s5p6450_gpios_4bit[] = { +#ifdef CONFIG_CPU_S5P6450 + { + .chip = { + .base = S5P6450_GPA(0), + .ngpio = S5P6450_GPIO_A_NR, + .label = "GPA", + }, + }, { + .chip = { + .base = S5P6450_GPB(0), + .ngpio = S5P6450_GPIO_B_NR, + .label = "GPB", + }, + }, { + .chip = { + .base = S5P6450_GPC(0), + .ngpio = S5P6450_GPIO_C_NR, + .label = "GPC", + }, + }, { + .chip = { + .base = S5P6450_GPD(0), + .ngpio = S5P6450_GPIO_D_NR, + .label = "GPD", + }, + }, { + .base = S5P6450_GPK_BASE, + .chip = { + .base = S5P6450_GPK(0), + .ngpio = S5P6450_GPIO_K_NR, + .label = "GPK", + }, + }, +#endif +}; + +static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = { +#ifdef CONFIG_CPU_S5P6450 + { + .base = S5P64X0_GPG_BASE + 0x4, + .chip = { + .base = S5P6450_GPG(0), + .ngpio = S5P6450_GPIO_G_NR, + .label = "GPG", + }, + }, { + .base = S5P64X0_GPH_BASE + 0x4, + .chip = { + .base = S5P6450_GPH(0), + .ngpio = S5P6450_GPIO_H_NR, + .label = "GPH", + }, + }, +#endif +}; + +static struct samsung_gpio_chip s5p6450_gpios_rbank[] = { +#ifdef CONFIG_CPU_S5P6450 + { + .base = S5P64X0_GPR_BASE + 0x4, + .config = &s5p64x0_gpio_cfg_rbank, + .chip = { + .base = S5P6450_GPR(0), + .ngpio = S5P6450_GPIO_R_NR, + .label = "GPR", + }, + }, +#endif +}; + +static struct samsung_gpio_chip s5p6450_gpios_2bit[] = { +#ifdef CONFIG_CPU_S5P6450 + { + .base = S5P64X0_GPF_BASE, + .config = &samsung_gpio_cfgs[6], + .chip = { + .base = S5P6450_GPF(0), + .ngpio = S5P6450_GPIO_F_NR, + .label = "GPF", + }, + }, { + .base = S5P64X0_GPI_BASE, + .config = &samsung_gpio_cfgs[4], + .chip = { + .base = S5P6450_GPI(0), + .ngpio = S5P6450_GPIO_I_NR, + .label = "GPI", + }, + }, { + .base = S5P64X0_GPJ_BASE, + .config = &samsung_gpio_cfgs[4], + .chip = { + .base = S5P6450_GPJ(0), + .ngpio = S5P6450_GPIO_J_NR, + .label = "GPJ", + }, + }, { + .base = S5P64X0_GPN_BASE, + .config = &samsung_gpio_cfgs[5], + .chip = { + .base = S5P6450_GPN(0), + .ngpio = S5P6450_GPIO_N_NR, + .label = "GPN", + }, + }, { + .base = S5P64X0_GPP_BASE, + .config = &samsung_gpio_cfgs[6], + .chip = { + .base = S5P6450_GPP(0), + .ngpio = S5P6450_GPIO_P_NR, + .label = "GPP", + }, + }, { + .base = S5P6450_GPQ_BASE, + .config = &samsung_gpio_cfgs[5], + .chip = { + .base = S5P6450_GPQ(0), + .ngpio = S5P6450_GPIO_Q_NR, + .label = "GPQ", + }, + }, { + .base = S5P6450_GPS_BASE, + .config = &samsung_gpio_cfgs[6], + .chip = { + .base = S5P6450_GPS(0), + .ngpio = S5P6450_GPIO_S_NR, + .label = "GPS", + }, + }, +#endif +}; + +/* + * S5PC100 GPIO bank summary: + * + * Bank GPIOs Style INT Type + * A0 8 4Bit GPIO_INT0 + * A1 5 4Bit GPIO_INT1 + * B 8 4Bit GPIO_INT2 + * C 5 4Bit GPIO_INT3 + * D 7 4Bit GPIO_INT4 + * E0 8 4Bit GPIO_INT5 + * E1 6 4Bit GPIO_INT6 + * F0 8 4Bit GPIO_INT7 + * F1 8 4Bit GPIO_INT8 + * F2 8 4Bit GPIO_INT9 + * F3 4 4Bit GPIO_INT10 + * G0 8 4Bit GPIO_INT11 + * G1 3 4Bit GPIO_INT12 + * G2 7 4Bit GPIO_INT13 + * G3 7 4Bit GPIO_INT14 + * H0 8 4Bit WKUP_INT + * H1 8 4Bit WKUP_INT + * H2 8 4Bit WKUP_INT + * H3 8 4Bit WKUP_INT + * I 8 4Bit GPIO_INT15 + * J0 8 4Bit GPIO_INT16 + * J1 5 4Bit GPIO_INT17 + * J2 8 4Bit GPIO_INT18 + * J3 8 4Bit GPIO_INT19 + * J4 4 4Bit GPIO_INT20 + * K0 8 4Bit None + * K1 6 4Bit None + * K2 8 4Bit None + * K3 8 4Bit None + * L0 8 4Bit None + * L1 8 4Bit None + * L2 8 4Bit None + * L3 8 4Bit None + */ + +static struct samsung_gpio_chip s5pc100_gpios_4bit[] = { +#ifdef CONFIG_CPU_S5PC100 + { + .chip = { + .base = S5PC100_GPA0(0), + .ngpio = S5PC100_GPIO_A0_NR, + .label = "GPA0", + }, + }, { + .chip = { + .base = S5PC100_GPA1(0), + .ngpio = S5PC100_GPIO_A1_NR, + .label = "GPA1", + }, + }, { + .chip = { + .base = S5PC100_GPB(0), + .ngpio = S5PC100_GPIO_B_NR, + .label = "GPB", + }, + }, { + .chip = { + .base = S5PC100_GPC(0), + .ngpio = S5PC100_GPIO_C_NR, + .label = "GPC", + }, + }, { + .chip = { + .base = S5PC100_GPD(0), + .ngpio = S5PC100_GPIO_D_NR, + .label = "GPD", + }, + }, { + .chip = { + .base = S5PC100_GPE0(0), + .ngpio = S5PC100_GPIO_E0_NR, + .label = "GPE0", + }, + }, { + .chip = { + .base = S5PC100_GPE1(0), + .ngpio = S5PC100_GPIO_E1_NR, + .label = "GPE1", + }, + }, { + .chip = { + .base = S5PC100_GPF0(0), + .ngpio = S5PC100_GPIO_F0_NR, + .label = "GPF0", + }, + }, { + .chip = { + .base = S5PC100_GPF1(0), + .ngpio = S5PC100_GPIO_F1_NR, + .label = "GPF1", + }, + }, { + .chip = { + .base = S5PC100_GPF2(0), + .ngpio = S5PC100_GPIO_F2_NR, + .label = "GPF2", + }, + }, { + .chip = { + .base = S5PC100_GPF3(0), + .ngpio = S5PC100_GPIO_F3_NR, + .label = "GPF3", + }, + }, { + .chip = { + .base = S5PC100_GPG0(0), + .ngpio = S5PC100_GPIO_G0_NR, + .label = "GPG0", + }, + }, { + .chip = { + .base = S5PC100_GPG1(0), + .ngpio = S5PC100_GPIO_G1_NR, + .label = "GPG1", + }, + }, { + .chip = { + .base = S5PC100_GPG2(0), + .ngpio = S5PC100_GPIO_G2_NR, + .label = "GPG2", + }, + }, { + .chip = { + .base = S5PC100_GPG3(0), + .ngpio = S5PC100_GPIO_G3_NR, + .label = "GPG3", + }, + }, { + .chip = { + .base = S5PC100_GPI(0), + .ngpio = S5PC100_GPIO_I_NR, + .label = "GPI", + }, + }, { + .chip = { + .base = S5PC100_GPJ0(0), + .ngpio = S5PC100_GPIO_J0_NR, + .label = "GPJ0", + }, + }, { + .chip = { + .base = S5PC100_GPJ1(0), + .ngpio = S5PC100_GPIO_J1_NR, + .label = "GPJ1", + }, + }, { + .chip = { + .base = S5PC100_GPJ2(0), + .ngpio = S5PC100_GPIO_J2_NR, + .label = "GPJ2", + }, + }, { + .chip = { + .base = S5PC100_GPJ3(0), + .ngpio = S5PC100_GPIO_J3_NR, + .label = "GPJ3", + }, + }, { + .chip = { + .base = S5PC100_GPJ4(0), + .ngpio = S5PC100_GPIO_J4_NR, + .label = "GPJ4", + }, + }, { + .chip = { + .base = S5PC100_GPK0(0), + .ngpio = S5PC100_GPIO_K0_NR, + .label = "GPK0", + }, + }, { + .chip = { + .base = S5PC100_GPK1(0), + .ngpio = S5PC100_GPIO_K1_NR, + .label = "GPK1", + }, + }, { + .chip = { + .base = S5PC100_GPK2(0), + .ngpio = S5PC100_GPIO_K2_NR, + .label = "GPK2", + }, + }, { + .chip = { + .base = S5PC100_GPK3(0), + .ngpio = S5PC100_GPIO_K3_NR, + .label = "GPK3", + }, + }, { + .chip = { + .base = S5PC100_GPL0(0), + .ngpio = S5PC100_GPIO_L0_NR, + .label = "GPL0", + }, + }, { + .chip = { + .base = S5PC100_GPL1(0), + .ngpio = S5PC100_GPIO_L1_NR, + .label = "GPL1", + }, + }, { + .chip = { + .base = S5PC100_GPL2(0), + .ngpio = S5PC100_GPIO_L2_NR, + .label = "GPL2", + }, + }, { + .chip = { + .base = S5PC100_GPL3(0), + .ngpio = S5PC100_GPIO_L3_NR, + .label = "GPL3", + }, + }, { + .chip = { + .base = S5PC100_GPL4(0), + .ngpio = S5PC100_GPIO_L4_NR, + .label = "GPL4", + }, + }, { + .base = (S5P_VA_GPIO + 0xC00), + .irq_base = IRQ_EINT(0), + .chip = { + .base = S5PC100_GPH0(0), + .ngpio = S5PC100_GPIO_H0_NR, + .label = "GPH0", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC20), + .irq_base = IRQ_EINT(8), + .chip = { + .base = S5PC100_GPH1(0), + .ngpio = S5PC100_GPIO_H1_NR, + .label = "GPH1", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC40), + .irq_base = IRQ_EINT(16), + .chip = { + .base = S5PC100_GPH2(0), + .ngpio = S5PC100_GPIO_H2_NR, + .label = "GPH2", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC60), + .irq_base = IRQ_EINT(24), + .chip = { + .base = S5PC100_GPH3(0), + .ngpio = S5PC100_GPIO_H3_NR, + .label = "GPH3", + .to_irq = samsung_gpiolib_to_irq, + }, + }, +#endif +}; + +/* + * Followings are the gpio banks in S5PV210/S5PC110 + * + * The 'config' member when left to NULL, is initialized to the default + * structure samsung_gpio_cfgs[3] in the init function below. + * + * The 'base' member is also initialized in the init function below. + * Note: The initialization of 'base' member of samsung_gpio_chip structure + * uses the above macro and depends on the banks being listed in order here. + */ + +static struct samsung_gpio_chip s5pv210_gpios_4bit[] = { +#ifdef CONFIG_CPU_S5PV210 + { + .chip = { + .base = S5PV210_GPA0(0), + .ngpio = S5PV210_GPIO_A0_NR, + .label = "GPA0", + }, + }, { + .chip = { + .base = S5PV210_GPA1(0), + .ngpio = S5PV210_GPIO_A1_NR, + .label = "GPA1", + }, + }, { + .chip = { + .base = S5PV210_GPB(0), + .ngpio = S5PV210_GPIO_B_NR, + .label = "GPB", + }, + }, { + .chip = { + .base = S5PV210_GPC0(0), + .ngpio = S5PV210_GPIO_C0_NR, + .label = "GPC0", + }, + }, { + .chip = { + .base = S5PV210_GPC1(0), + .ngpio = S5PV210_GPIO_C1_NR, + .label = "GPC1", + }, + }, { + .chip = { + .base = S5PV210_GPD0(0), + .ngpio = S5PV210_GPIO_D0_NR, + .label = "GPD0", + }, + }, { + .chip = { + .base = S5PV210_GPD1(0), + .ngpio = S5PV210_GPIO_D1_NR, + .label = "GPD1", + }, + }, { + .chip = { + .base = S5PV210_GPE0(0), + .ngpio = S5PV210_GPIO_E0_NR, + .label = "GPE0", + }, + }, { + .chip = { + .base = S5PV210_GPE1(0), + .ngpio = S5PV210_GPIO_E1_NR, + .label = "GPE1", + }, + }, { + .chip = { + .base = S5PV210_GPF0(0), + .ngpio = S5PV210_GPIO_F0_NR, + .label = "GPF0", + }, + }, { + .chip = { + .base = S5PV210_GPF1(0), + .ngpio = S5PV210_GPIO_F1_NR, + .label = "GPF1", + }, + }, { + .chip = { + .base = S5PV210_GPF2(0), + .ngpio = S5PV210_GPIO_F2_NR, + .label = "GPF2", + }, + }, { + .chip = { + .base = S5PV210_GPF3(0), + .ngpio = S5PV210_GPIO_F3_NR, + .label = "GPF3", + }, + }, { + .chip = { + .base = S5PV210_GPG0(0), + .ngpio = S5PV210_GPIO_G0_NR, + .label = "GPG0", + }, + }, { + .chip = { + .base = S5PV210_GPG1(0), + .ngpio = S5PV210_GPIO_G1_NR, + .label = "GPG1", + }, + }, { + .chip = { + .base = S5PV210_GPG2(0), + .ngpio = S5PV210_GPIO_G2_NR, + .label = "GPG2", + }, + }, { + .chip = { + .base = S5PV210_GPG3(0), + .ngpio = S5PV210_GPIO_G3_NR, + .label = "GPG3", + }, + }, { + .chip = { + .base = S5PV210_GPI(0), + .ngpio = S5PV210_GPIO_I_NR, + .label = "GPI", + }, + }, { + .chip = { + .base = S5PV210_GPJ0(0), + .ngpio = S5PV210_GPIO_J0_NR, + .label = "GPJ0", + }, + }, { + .chip = { + .base = S5PV210_GPJ1(0), + .ngpio = S5PV210_GPIO_J1_NR, + .label = "GPJ1", + }, + }, { + .chip = { + .base = S5PV210_GPJ2(0), + .ngpio = S5PV210_GPIO_J2_NR, + .label = "GPJ2", + }, + }, { + .chip = { + .base = S5PV210_GPJ3(0), + .ngpio = S5PV210_GPIO_J3_NR, + .label = "GPJ3", + }, + }, { + .chip = { + .base = S5PV210_GPJ4(0), + .ngpio = S5PV210_GPIO_J4_NR, + .label = "GPJ4", + }, + }, { + .chip = { + .base = S5PV210_MP01(0), + .ngpio = S5PV210_GPIO_MP01_NR, + .label = "MP01", + }, + }, { + .chip = { + .base = S5PV210_MP02(0), + .ngpio = S5PV210_GPIO_MP02_NR, + .label = "MP02", + }, + }, { + .chip = { + .base = S5PV210_MP03(0), + .ngpio = S5PV210_GPIO_MP03_NR, + .label = "MP03", + }, + }, { + .chip = { + .base = S5PV210_MP04(0), + .ngpio = S5PV210_GPIO_MP04_NR, + .label = "MP04", + }, + }, { + .chip = { + .base = S5PV210_MP05(0), + .ngpio = S5PV210_GPIO_MP05_NR, + .label = "MP05", + }, + }, { + .base = (S5P_VA_GPIO + 0xC00), + .irq_base = IRQ_EINT(0), + .chip = { + .base = S5PV210_GPH0(0), + .ngpio = S5PV210_GPIO_H0_NR, + .label = "GPH0", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC20), + .irq_base = IRQ_EINT(8), + .chip = { + .base = S5PV210_GPH1(0), + .ngpio = S5PV210_GPIO_H1_NR, + .label = "GPH1", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC40), + .irq_base = IRQ_EINT(16), + .chip = { + .base = S5PV210_GPH2(0), + .ngpio = S5PV210_GPIO_H2_NR, + .label = "GPH2", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO + 0xC60), + .irq_base = IRQ_EINT(24), + .chip = { + .base = S5PV210_GPH3(0), + .ngpio = S5PV210_GPIO_H3_NR, + .label = "GPH3", + .to_irq = samsung_gpiolib_to_irq, + }, + }, +#endif +}; + +/* + * Followings are the gpio banks in EXYNOS4210 + * + * The 'config' member when left to NULL, is initialized to the default + * structure samsung_gpio_cfgs[3] in the init function below. + * + * The 'base' member is also initialized in the init function below. + * Note: The initialization of 'base' member of samsung_gpio_chip structure + * uses the above macro and depends on the banks being listed in order here. + */ + +static struct samsung_gpio_chip exynos4_gpios_1[] = { +#ifdef CONFIG_ARCH_EXYNOS4 + { + .chip = { + .base = EXYNOS4_GPA0(0), + .ngpio = EXYNOS4_GPIO_A0_NR, + .label = "GPA0", + }, + }, { + .chip = { + .base = EXYNOS4_GPA1(0), + .ngpio = EXYNOS4_GPIO_A1_NR, + .label = "GPA1", + }, + }, { + .chip = { + .base = EXYNOS4_GPB(0), + .ngpio = EXYNOS4_GPIO_B_NR, + .label = "GPB", + }, + }, { + .chip = { + .base = EXYNOS4_GPC0(0), + .ngpio = EXYNOS4_GPIO_C0_NR, + .label = "GPC0", + }, + }, { + .chip = { + .base = EXYNOS4_GPC1(0), + .ngpio = EXYNOS4_GPIO_C1_NR, + .label = "GPC1", + }, + }, { + .chip = { + .base = EXYNOS4_GPD0(0), + .ngpio = EXYNOS4_GPIO_D0_NR, + .label = "GPD0", + }, + }, { + .chip = { + .base = EXYNOS4_GPD1(0), + .ngpio = EXYNOS4_GPIO_D1_NR, + .label = "GPD1", + }, + }, { + .chip = { + .base = EXYNOS4_GPE0(0), + .ngpio = EXYNOS4_GPIO_E0_NR, + .label = "GPE0", + }, + }, { + .chip = { + .base = EXYNOS4_GPE1(0), + .ngpio = EXYNOS4_GPIO_E1_NR, + .label = "GPE1", + }, + }, { + .chip = { + .base = EXYNOS4_GPE2(0), + .ngpio = EXYNOS4_GPIO_E2_NR, + .label = "GPE2", + }, + }, { + .chip = { + .base = EXYNOS4_GPE3(0), + .ngpio = EXYNOS4_GPIO_E3_NR, + .label = "GPE3", + }, + }, { + .chip = { + .base = EXYNOS4_GPE4(0), + .ngpio = EXYNOS4_GPIO_E4_NR, + .label = "GPE4", + }, + }, { + .chip = { + .base = EXYNOS4_GPF0(0), + .ngpio = EXYNOS4_GPIO_F0_NR, + .label = "GPF0", + }, + }, { + .chip = { + .base = EXYNOS4_GPF1(0), + .ngpio = EXYNOS4_GPIO_F1_NR, + .label = "GPF1", + }, + }, { + .chip = { + .base = EXYNOS4_GPF2(0), + .ngpio = EXYNOS4_GPIO_F2_NR, + .label = "GPF2", + }, + }, { + .chip = { + .base = EXYNOS4_GPF3(0), + .ngpio = EXYNOS4_GPIO_F3_NR, + .label = "GPF3", + }, + }, +#endif +}; + +static struct samsung_gpio_chip exynos4_gpios_2[] = { +#ifdef CONFIG_ARCH_EXYNOS4 + { + .chip = { + .base = EXYNOS4_GPJ0(0), + .ngpio = EXYNOS4_GPIO_J0_NR, + .label = "GPJ0", + }, + }, { + .chip = { + .base = EXYNOS4_GPJ1(0), + .ngpio = EXYNOS4_GPIO_J1_NR, + .label = "GPJ1", + }, + }, { + .chip = { + .base = EXYNOS4_GPK0(0), + .ngpio = EXYNOS4_GPIO_K0_NR, + .label = "GPK0", + }, + }, { + .chip = { + .base = EXYNOS4_GPK1(0), + .ngpio = EXYNOS4_GPIO_K1_NR, + .label = "GPK1", + }, + }, { + .chip = { + .base = EXYNOS4_GPK2(0), + .ngpio = EXYNOS4_GPIO_K2_NR, + .label = "GPK2", + }, + }, { + .chip = { + .base = EXYNOS4_GPK3(0), + .ngpio = EXYNOS4_GPIO_K3_NR, + .label = "GPK3", + }, + }, { + .chip = { + .base = EXYNOS4_GPL0(0), + .ngpio = EXYNOS4_GPIO_L0_NR, + .label = "GPL0", + }, + }, { + .chip = { + .base = EXYNOS4_GPL1(0), + .ngpio = EXYNOS4_GPIO_L1_NR, + .label = "GPL1", + }, + }, { + .chip = { + .base = EXYNOS4_GPL2(0), + .ngpio = EXYNOS4_GPIO_L2_NR, + .label = "GPL2", + }, + }, { + .config = &samsung_gpio_cfgs[0], + .chip = { + .base = EXYNOS4_GPY0(0), + .ngpio = EXYNOS4_GPIO_Y0_NR, + .label = "GPY0", + }, + }, { + .config = &samsung_gpio_cfgs[0], + .chip = { + .base = EXYNOS4_GPY1(0), + .ngpio = EXYNOS4_GPIO_Y1_NR, + .label = "GPY1", + }, + }, { + .config = &samsung_gpio_cfgs[0], + .chip = { + .base = EXYNOS4_GPY2(0), + .ngpio = EXYNOS4_GPIO_Y2_NR, + .label = "GPY2", + }, + }, { + .config = &samsung_gpio_cfgs[0], + .chip = { + .base = EXYNOS4_GPY3(0), + .ngpio = EXYNOS4_GPIO_Y3_NR, + .label = "GPY3", + }, + }, { + .config = &samsung_gpio_cfgs[0], + .chip = { + .base = EXYNOS4_GPY4(0), + .ngpio = EXYNOS4_GPIO_Y4_NR, + .label = "GPY4", + }, + }, { + .config = &samsung_gpio_cfgs[0], + .chip = { + .base = EXYNOS4_GPY5(0), + .ngpio = EXYNOS4_GPIO_Y5_NR, + .label = "GPY5", + }, + }, { + .config = &samsung_gpio_cfgs[0], + .chip = { + .base = EXYNOS4_GPY6(0), + .ngpio = EXYNOS4_GPIO_Y6_NR, + .label = "GPY6", + }, + }, { + .base = (S5P_VA_GPIO2 + 0xC00), + .config = &samsung_gpio_cfgs[3], + .irq_base = IRQ_EINT(0), + .chip = { + .base = EXYNOS4_GPX0(0), + .ngpio = EXYNOS4_GPIO_X0_NR, + .label = "GPX0", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO2 + 0xC20), + .config = &samsung_gpio_cfgs[3], + .irq_base = IRQ_EINT(8), + .chip = { + .base = EXYNOS4_GPX1(0), + .ngpio = EXYNOS4_GPIO_X1_NR, + .label = "GPX1", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO2 + 0xC40), + .config = &samsung_gpio_cfgs[3], + .irq_base = IRQ_EINT(16), + .chip = { + .base = EXYNOS4_GPX2(0), + .ngpio = EXYNOS4_GPIO_X2_NR, + .label = "GPX2", + .to_irq = samsung_gpiolib_to_irq, + }, + }, { + .base = (S5P_VA_GPIO2 + 0xC60), + .config = &samsung_gpio_cfgs[3], + .irq_base = IRQ_EINT(24), + .chip = { + .base = EXYNOS4_GPX3(0), + .ngpio = EXYNOS4_GPIO_X3_NR, + .label = "GPX3", + .to_irq = samsung_gpiolib_to_irq, + }, + }, +#endif +}; + +static struct samsung_gpio_chip exynos4_gpios_3[] = { +#ifdef CONFIG_ARCH_EXYNOS4 + { + .chip = { + .base = EXYNOS4_GPZ(0), + .ngpio = EXYNOS4_GPIO_Z_NR, + .label = "GPZ", + }, + }, +#endif +}; + +/* TODO: cleanup soc_is_* */ +static __init int samsung_gpiolib_init(void) +{ + struct samsung_gpio_chip *chip; + int i, nr_chips; + int group = 0; + + samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); + + if (soc_is_s3c24xx()) { + s3c24xx_gpiolib_add_chips(s3c24xx_gpios, + ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO); + } else if (soc_is_s3c64xx()) { + samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit, + ARRAY_SIZE(s3c64xx_gpios_2bit), + S3C64XX_VA_GPIO + 0xE0, 0x20); + samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit, + ARRAY_SIZE(s3c64xx_gpios_4bit), + S3C64XX_VA_GPIO); + samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2, + ARRAY_SIZE(s3c64xx_gpios_4bit2)); + } else if (soc_is_s5p6440()) { + samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit, + ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0); + samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit, + ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO); + samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2, + ARRAY_SIZE(s5p6440_gpios_4bit2)); + s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank, + ARRAY_SIZE(s5p6440_gpios_rbank)); + } else if (soc_is_s5p6450()) { + samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit, + ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0); + samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit, + ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO); + samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2, + ARRAY_SIZE(s5p6450_gpios_4bit2)); + s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank, + ARRAY_SIZE(s5p6450_gpios_rbank)); + } else if (soc_is_s5pc100()) { + group = 0; + chip = s5pc100_gpios_4bit; + nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit); + + for (i = 0; i < nr_chips; i++, chip++) { + if (!chip->config) { + chip->config = &samsung_gpio_cfgs[3]; + chip->group = group++; + } + } + samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO); +#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT) + s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); +#endif + } else if (soc_is_s5pv210()) { + group = 0; + chip = s5pv210_gpios_4bit; + nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit); + + for (i = 0; i < nr_chips; i++, chip++) { + if (!chip->config) { + chip->config = &samsung_gpio_cfgs[3]; + chip->group = group++; + } + } + samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO); +#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT) + s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); +#endif + } else if (soc_is_exynos4210()) { + group = 0; + + /* gpio part1 */ + chip = exynos4_gpios_1; + nr_chips = ARRAY_SIZE(exynos4_gpios_1); + + for (i = 0; i < nr_chips; i++, chip++) { + if (!chip->config) { + chip->config = &exynos4_gpio_cfg; + chip->group = group++; + } + } + samsung_gpiolib_add_4bit_chips(exynos4_gpios_1, nr_chips, S5P_VA_GPIO1); + + /* gpio part2 */ + chip = exynos4_gpios_2; + nr_chips = ARRAY_SIZE(exynos4_gpios_2); + + for (i = 0; i < nr_chips; i++, chip++) { + if (!chip->config) { + chip->config = &exynos4_gpio_cfg; + chip->group = group++; + } + } + samsung_gpiolib_add_4bit_chips(exynos4_gpios_2, nr_chips, S5P_VA_GPIO2); + + /* gpio part3 */ + chip = exynos4_gpios_3; + nr_chips = ARRAY_SIZE(exynos4_gpios_3); + + for (i = 0; i < nr_chips; i++, chip++) { + if (!chip->config) { + chip->config = &exynos4_gpio_cfg; + chip->group = group++; + } + } + samsung_gpiolib_add_4bit_chips(exynos4_gpios_3, nr_chips, S5P_VA_GPIO3); + +#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT) + s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS); + s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS); +#endif + } + + return 0; +} +core_initcall(samsung_gpiolib_init); + +int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) +{ + struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); + unsigned long flags; + int offset; + int ret; + + if (!chip) + return -EINVAL; + + offset = pin - chip->chip.base; + + samsung_gpio_lock(chip, flags); + ret = samsung_gpio_do_setcfg(chip, offset, config); + samsung_gpio_unlock(chip, flags); + + return ret; +} +EXPORT_SYMBOL(s3c_gpio_cfgpin); + +int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, + unsigned int cfg) +{ + int ret; + + for (; nr > 0; nr--, start++) { + ret = s3c_gpio_cfgpin(start, cfg); + if (ret != 0) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range); + +int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, + unsigned int cfg, samsung_gpio_pull_t pull) +{ + int ret; + + for (; nr > 0; nr--, start++) { + s3c_gpio_setpull(start, pull); + ret = s3c_gpio_cfgpin(start, cfg); + if (ret != 0) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range); + +unsigned s3c_gpio_getcfg(unsigned int pin) +{ + struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); + unsigned long flags; + unsigned ret = 0; + int offset; + + if (chip) { + offset = pin - chip->chip.base; + + samsung_gpio_lock(chip, flags); + ret = samsung_gpio_do_getcfg(chip, offset); + samsung_gpio_unlock(chip, flags); + } + + return ret; +} +EXPORT_SYMBOL(s3c_gpio_getcfg); + +int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull) +{ + struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); + unsigned long flags; + int offset, ret; + + if (!chip) + return -EINVAL; + + offset = pin - chip->chip.base; + + samsung_gpio_lock(chip, flags); + ret = samsung_gpio_do_setpull(chip, offset, pull); + samsung_gpio_unlock(chip, flags); + + return ret; +} +EXPORT_SYMBOL(s3c_gpio_setpull); + +samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin) +{ + struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); + unsigned long flags; + int offset; + u32 pup = 0; + + if (chip) { + offset = pin - chip->chip.base; + + samsung_gpio_lock(chip, flags); + pup = samsung_gpio_do_getpull(chip, offset); + samsung_gpio_unlock(chip, flags); + } + + return (__force samsung_gpio_pull_t)pup; +} +EXPORT_SYMBOL(s3c_gpio_getpull); + +/* gpiolib wrappers until these are totally eliminated */ + +void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) +{ + int ret; + + WARN_ON(to); /* should be none of these left */ + + if (!to) { + /* if pull is enabled, try first with up, and if that + * fails, try using down */ + + ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP); + if (ret) + s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN); + } else { + s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE); + } +} +EXPORT_SYMBOL(s3c2410_gpio_pullup); + +void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) +{ + /* do this via gpiolib until all users removed */ + + gpio_request(pin, "temporary"); + gpio_set_value(pin, to); + gpio_free(pin); +} +EXPORT_SYMBOL(s3c2410_gpio_setpin); + +unsigned int s3c2410_gpio_getpin(unsigned int pin) +{ + struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); + unsigned long offs = pin - chip->chip.base; + + return __raw_readl(chip->base + 0x04) & (1 << offs); +} +EXPORT_SYMBOL(s3c2410_gpio_getpin); + +#ifdef CONFIG_S5P_GPIO_DRVSTR +s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin) +{ + struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); + unsigned int off; + void __iomem *reg; + int shift; + u32 drvstr; + + if (!chip) + return -EINVAL; + + off = pin - chip->chip.base; + shift = off * 2; + reg = chip->base + 0x0C; + + drvstr = __raw_readl(reg); + drvstr = drvstr >> shift; + drvstr &= 0x3; + + return (__force s5p_gpio_drvstr_t)drvstr; +} +EXPORT_SYMBOL(s5p_gpio_get_drvstr); + +int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr) +{ + struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); + unsigned int off; + void __iomem *reg; + int shift; + u32 tmp; + + if (!chip) + return -EINVAL; + + off = pin - chip->chip.base; + shift = off * 2; + reg = chip->base + 0x0C; + + tmp = __raw_readl(reg); + tmp &= ~(0x3 << shift); + tmp |= drvstr << shift; + + __raw_writel(tmp, reg); + + return 0; +} +EXPORT_SYMBOL(s5p_gpio_set_drvstr); +#endif /* CONFIG_S5P_GPIO_DRVSTR */ + +#ifdef CONFIG_PLAT_S3C24XX +unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) +{ + unsigned long flags; + unsigned long misccr; + + local_irq_save(flags); + misccr = __raw_readl(S3C24XX_MISCCR); + misccr &= ~clear; + misccr ^= change; + __raw_writel(misccr, S3C24XX_MISCCR); + local_irq_restore(flags); + + return misccr; +} +EXPORT_SYMBOL(s3c2410_modify_misccr); +#endif diff --git a/sound/soc/samsung/dma.c b/sound/soc/samsung/dma.c index 851346f7d68d..2d622b635e68 100644 --- a/sound/soc/samsung/dma.c +++ b/sound/soc/samsung/dma.c @@ -198,10 +198,10 @@ static int dma_hw_free(struct snd_pcm_substream *substream) pr_debug("Entered %s\n", __func__); - /* TODO - do we need to ensure DMA flushed */ snd_pcm_set_runtime_buffer(substream, NULL); if (prtd->params) { + prtd->params->ops->flush(prtd->params->ch); prtd->params->ops->release(prtd->params->ch, prtd->params->client); prtd->params = NULL; |