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-rw-r--r--arch/arm/mach-sunxi/Kconfig2
-rw-r--r--arch/arm64/Kconfig.platforms2
-rw-r--r--drivers/irqchip/Makefile1
-rw-r--r--drivers/irqchip/irq-sun6i-r.c284
-rw-r--r--drivers/irqchip/irq-sunxi-nmi.c26
5 files changed, 292 insertions, 23 deletions
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index eeadb1a4dcfe..e5c2fce281cd 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -6,6 +6,8 @@ menuconfig ARCH_SUNXI
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select GPIOLIB
+ select IRQ_DOMAIN_HIERARCHY
+ select IRQ_FASTEOI_HIERARCHY_HANDLERS
select PINCTRL
select PM_OPP
select SUN4I_TIMER
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6eecdef538bd..f2aa1518c6f4 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -17,6 +17,8 @@ config ARCH_SUNXI
bool "Allwinner sunxi 64-bit SoC Family"
select ARCH_HAS_RESET_CONTROLLER
select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN_HIERARCHY
+ select IRQ_FASTEOI_HIERARCHY_HANDLERS
select PINCTRL
select RESET_CONTROLLER
help
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 37e3556df127..2a1994d7f99a 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
+obj-$(CONFIG_ARCH_SUNXI) += irq-sun6i-r.o
obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c
new file mode 100644
index 000000000000..284b56905eb7
--- /dev/null
+++ b/drivers/irqchip/irq-sun6i-r.c
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * The R_INTC in Allwinner A31 and newer SoCs manages several types of
+ * interrupts, as shown below:
+ *
+ * NMI IRQ DIRECT IRQs MUXED IRQs
+ * bit 0 bits 1-15^ bits 19-31
+ *
+ * +---------+ +---------+ +---------+ +---------+
+ * | NMI Pad | | IRQ d | | IRQ m | | IRQ m+7 |
+ * +---------+ +---------+ +---------+ +---------+
+ * | | | | | | |
+ * | | | | |......| |
+ * +------V------+ +------------+ | | | +--V------V--+ |
+ * | Invert/ | | Write 1 to | | | | | AND with | |
+ * | Edge Detect | | PENDING[0] | | | | | MUX[m/8] | |
+ * +-------------+ +------------+ | | | +------------+ |
+ * | | | | | | |
+ * +--V-------V--+ +--V--+ | +--V--+ | +--V--+
+ * | Set Reset| | GIC | | | GIC | | | GIC |
+ * | Latch | | SPI | | | SPI |... | ...| SPI |
+ * +-------------+ | N+d | | | m | | | m+7 |
+ * | | +-----+ | +-----+ | +-----+
+ * | | | |
+ * +-------V-+ +-V----------+ +---------V--+ +--------V--------+
+ * | GIC SPI | | AND with | | AND with | | AND with |
+ * | N (=32) | | ENABLE[0] | | ENABLE[d] | | ENABLE[19+m/8] |
+ * +---------+ +------------+ +------------+ +-----------------+
+ * | | |
+ * +------V-----+ +------V-----+ +--------V--------+
+ * | Read | | Read | | Read |
+ * | PENDING[0] | | PENDING[d] | | PENDING[19+m/8] |
+ * +------------+ +------------+ +-----------------+
+ *
+ * ^ bits 16-18 are direct IRQs for peripherals with banked interrupts, such as
+ * the MSGBOX. These IRQs do not map to any GIC SPI.
+ *
+ * The H6 variant adds two more (banked) direct IRQs and implements the full
+ * set of 128 mux bits. This requires a second set of top-level registers.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define SUN6I_NMI_CTRL (0x0c)
+#define SUN6I_IRQ_PENDING(n) (0x10 + 4 * (n))
+#define SUN6I_IRQ_ENABLE(n) (0x40 + 4 * (n))
+#define SUN6I_MUX_ENABLE(n) (0xc0 + 4 * (n))
+
+#define SUN6I_NMI_SRC_TYPE_LEVEL_LOW 0
+#define SUN6I_NMI_SRC_TYPE_EDGE_FALLING 1
+#define SUN6I_NMI_SRC_TYPE_LEVEL_HIGH 2
+#define SUN6I_NMI_SRC_TYPE_EDGE_RISING 3
+
+#define SUN6I_NMI_BIT BIT(0)
+
+#define SUN6I_NMI_NEEDS_ACK ((void *)1)
+
+#define SUN6I_NR_TOP_LEVEL_IRQS 64
+#define SUN6I_NR_DIRECT_IRQS 16
+#define SUN6I_NR_MUX_BITS 128
+
+static void __iomem *base;
+static irq_hw_number_t nmi_hwirq;
+
+static void sun6i_r_intc_ack_nmi(void)
+{
+ writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0));
+}
+
+static void sun6i_r_intc_nmi_ack(struct irq_data *data)
+{
+ if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
+ sun6i_r_intc_ack_nmi();
+ else
+ data->chip_data = SUN6I_NMI_NEEDS_ACK;
+}
+
+static void sun6i_r_intc_nmi_eoi(struct irq_data *data)
+{
+ /* For oneshot IRQs, delay the ack until the IRQ is unmasked. */
+ if (data->chip_data == SUN6I_NMI_NEEDS_ACK && !irqd_irq_masked(data)) {
+ data->chip_data = NULL;
+ sun6i_r_intc_ack_nmi();
+ }
+
+ irq_chip_eoi_parent(data);
+}
+
+static void sun6i_r_intc_nmi_unmask(struct irq_data *data)
+{
+ if (data->chip_data == SUN6I_NMI_NEEDS_ACK) {
+ data->chip_data = NULL;
+ sun6i_r_intc_ack_nmi();
+ }
+
+ irq_chip_unmask_parent(data);
+}
+
+static int sun6i_r_intc_nmi_set_type(struct irq_data *data, unsigned int type)
+{
+ u32 nmi_src_type;
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ nmi_src_type = SUN6I_NMI_SRC_TYPE_EDGE_RISING;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ nmi_src_type = SUN6I_NMI_SRC_TYPE_EDGE_FALLING;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ nmi_src_type = SUN6I_NMI_SRC_TYPE_LEVEL_HIGH;
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ nmi_src_type = SUN6I_NMI_SRC_TYPE_LEVEL_LOW;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ writel_relaxed(nmi_src_type, base + SUN6I_NMI_CTRL);
+
+ /*
+ * The "External NMI" GIC input connects to a latch inside R_INTC, not
+ * directly to the pin. So the GIC trigger type does not depend on the
+ * NMI pin trigger type.
+ */
+ return irq_chip_set_type_parent(data, IRQ_TYPE_LEVEL_HIGH);
+}
+
+static int sun6i_r_intc_nmi_set_irqchip_state(struct irq_data *data,
+ enum irqchip_irq_state which,
+ bool state)
+{
+ if (which == IRQCHIP_STATE_PENDING && !state)
+ sun6i_r_intc_ack_nmi();
+
+ return irq_chip_set_parent_state(data, which, state);
+}
+
+static struct irq_chip sun6i_r_intc_nmi_chip = {
+ .name = "sun6i-r-intc",
+ .irq_ack = sun6i_r_intc_nmi_ack,
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = sun6i_r_intc_nmi_unmask,
+ .irq_eoi = sun6i_r_intc_nmi_eoi,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .irq_set_type = sun6i_r_intc_nmi_set_type,
+ .irq_set_irqchip_state = sun6i_r_intc_nmi_set_irqchip_state,
+ .flags = IRQCHIP_SET_TYPE_MASKED |
+ IRQCHIP_SKIP_SET_WAKE,
+};
+
+static int sun6i_r_intc_domain_translate(struct irq_domain *domain,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ /* Accept the old two-cell binding for the NMI only. */
+ if (fwspec->param_count == 2 && fwspec->param[0] == 0) {
+ *hwirq = nmi_hwirq;
+ *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
+ return 0;
+ }
+
+ /* Otherwise this binding should match the GIC SPI binding. */
+ if (fwspec->param_count < 3)
+ return -EINVAL;
+ if (fwspec->param[0] != GIC_SPI)
+ return -EINVAL;
+
+ *hwirq = fwspec->param[1];
+ *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
+
+ return 0;
+}
+
+static int sun6i_r_intc_domain_alloc(struct irq_domain *domain,
+ unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ struct irq_fwspec *fwspec = arg;
+ struct irq_fwspec gic_fwspec;
+ unsigned long hwirq;
+ unsigned int type;
+ int i, ret;
+
+ ret = sun6i_r_intc_domain_translate(domain, fwspec, &hwirq, &type);
+ if (ret)
+ return ret;
+ if (hwirq + nr_irqs > SUN6I_NR_MUX_BITS)
+ return -EINVAL;
+
+ /* Construct a GIC-compatible fwspec from this fwspec. */
+ gic_fwspec = (struct irq_fwspec) {
+ .fwnode = domain->parent->fwnode,
+ .param_count = 3,
+ .param = { GIC_SPI, hwirq, type },
+ };
+
+ ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_fwspec);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < nr_irqs; ++i, ++hwirq, ++virq) {
+ if (hwirq == nmi_hwirq) {
+ irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
+ &sun6i_r_intc_nmi_chip, 0);
+ irq_set_handler(virq, handle_fasteoi_ack_irq);
+ } else {
+ /* Only the NMI is currently supported. */
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static const struct irq_domain_ops sun6i_r_intc_domain_ops = {
+ .translate = sun6i_r_intc_domain_translate,
+ .alloc = sun6i_r_intc_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+};
+
+static void sun6i_r_intc_resume(void)
+{
+ int i;
+
+ /* Only the NMI is relevant during normal operation. */
+ writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_ENABLE(0));
+ for (i = 1; i < BITS_TO_U32(SUN6I_NR_TOP_LEVEL_IRQS); ++i)
+ writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i));
+}
+
+static int __init sun6i_r_intc_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct irq_domain *domain, *parent_domain;
+ struct of_phandle_args nmi_parent;
+ int ret;
+
+ /* Extract the NMI hwirq number from the OF node. */
+ ret = of_irq_parse_one(node, 0, &nmi_parent);
+ if (ret)
+ return ret;
+ if (nmi_parent.args_count < 3 ||
+ nmi_parent.args[0] != GIC_SPI ||
+ nmi_parent.args[2] != IRQ_TYPE_LEVEL_HIGH)
+ return -EINVAL;
+ nmi_hwirq = nmi_parent.args[1];
+
+ parent_domain = irq_find_host(parent);
+ if (!parent_domain) {
+ pr_err("%pOF: Failed to obtain parent domain\n", node);
+ return -ENXIO;
+ }
+
+ base = of_io_request_and_map(node, 0, NULL);
+ if (IS_ERR(base)) {
+ pr_err("%pOF: Failed to map MMIO region\n", node);
+ return PTR_ERR(base);
+ }
+
+ domain = irq_domain_add_hierarchy(parent_domain, 0, 0, node,
+ &sun6i_r_intc_domain_ops, NULL);
+ if (!domain) {
+ pr_err("%pOF: Failed to allocate domain\n", node);
+ iounmap(base);
+ return -ENOMEM;
+ }
+
+ sun6i_r_intc_ack_nmi();
+ sun6i_r_intc_resume();
+
+ return 0;
+}
+IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_r_intc_init);
diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index a412b5d5d0fa..9f2bd0c5d289 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -27,18 +27,12 @@
#define SUNXI_NMI_IRQ_BIT BIT(0)
-#define SUN6I_R_INTC_CTRL 0x0c
-#define SUN6I_R_INTC_PENDING 0x10
-#define SUN6I_R_INTC_ENABLE 0x40
-
/*
* For deprecated sun6i-a31-sc-nmi compatible.
- * Registers are offset by 0x0c.
*/
-#define SUN6I_R_INTC_NMI_OFFSET 0x0c
-#define SUN6I_NMI_CTRL (SUN6I_R_INTC_CTRL - SUN6I_R_INTC_NMI_OFFSET)
-#define SUN6I_NMI_PENDING (SUN6I_R_INTC_PENDING - SUN6I_R_INTC_NMI_OFFSET)
-#define SUN6I_NMI_ENABLE (SUN6I_R_INTC_ENABLE - SUN6I_R_INTC_NMI_OFFSET)
+#define SUN6I_NMI_CTRL 0x00
+#define SUN6I_NMI_PENDING 0x04
+#define SUN6I_NMI_ENABLE 0x34
#define SUN7I_NMI_CTRL 0x00
#define SUN7I_NMI_PENDING 0x04
@@ -61,12 +55,6 @@ struct sunxi_sc_nmi_reg_offs {
u32 enable;
};
-static const struct sunxi_sc_nmi_reg_offs sun6i_r_intc_reg_offs __initconst = {
- .ctrl = SUN6I_R_INTC_CTRL,
- .pend = SUN6I_R_INTC_PENDING,
- .enable = SUN6I_R_INTC_ENABLE,
-};
-
static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = {
.ctrl = SUN6I_NMI_CTRL,
.pend = SUN6I_NMI_PENDING,
@@ -232,14 +220,6 @@ fail_irqd_remove:
return ret;
}
-static int __init sun6i_r_intc_irq_init(struct device_node *node,
- struct device_node *parent)
-{
- return sunxi_sc_nmi_irq_init(node, &sun6i_r_intc_reg_offs);
-}
-IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc",
- sun6i_r_intc_irq_init);
-
static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
struct device_node *parent)
{