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authorDave Jiang <dave.jiang@intel.com>2023-01-06 09:39:49 -0700
committerDan Williams <dan.j.williams@intel.com>2023-01-09 12:55:54 -0800
commit2ec1b17f745b08526220f3c169d2eb9799a9be39 (patch)
tree39c3f0fc88c10a99bf28d7ac100e81393763e0ce /usr/dummy-include
parentb7bfaa761d760e72a969d116517eaa12e404c262 (diff)
downloadlinux-2ec1b17f745b08526220f3c169d2eb9799a9be39.tar.bz2
cxl: fix cxl_report_and_clear() RAS UE addr mis-assignment
'addr' that contains RAS UE register address is re-assigned to RAS_CAP_CONTROL offset if there are multiple UE errors. Use different addr variable to avoid the reassignment mistake. Fixes: 2905cb5236cb ("cxl/pci: Add (hopeful) error handling support") Reported-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://lore.kernel.org/r/167302318779.580155.15233596744650706167.stgit@djiang5-mobl3.local Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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