diff options
| author | Ian Rogers <irogers@google.com> | 2022-12-14 22:55:01 -0800 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2022-12-21 14:52:41 -0300 |
| commit | 28641ef5f387f2c8f57a7273d1ce35d168f14f86 (patch) | |
| tree | d4b669369cb7a7686d3fac62d248e3d4a232c78f /tools/perf/pmu-events/arch/x86/sandybridge/other.json | |
| parent | d4e50e519ba0af3ab961de74bd88366ea11f3e62 (diff) | |
| download | linux-28641ef5f387f2c8f57a7273d1ce35d168f14f86.tar.bz2 | |
perf vendor events intel: Refresh sandybridge metrics and events
Update the sandybridge metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
events are unchanged but unused json values are removed. The
formatting changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
Acked-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215065510.1621979-15-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/sandybridge/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/sandybridge/other.json | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/other.json b/tools/perf/pmu-events/arch/x86/sandybridge/other.json index 2f873ab14156..9f96121baef8 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/other.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/other.json @@ -1,8 +1,6 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", @@ -10,8 +8,6 @@ }, { "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -21,8 +17,6 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", @@ -30,8 +24,6 @@ }, { "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x4E", "EventName": "HW_PRE_REQ.DL1_MISS", "SampleAfterValue": "2000003", @@ -39,8 +31,6 @@ }, { "BriefDescription": "Valid instructions written to IQ per cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x17", "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", "SampleAfterValue": "2000003", @@ -48,8 +38,6 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "SampleAfterValue": "2000003", |