diff options
author | Ian Rogers <irogers@google.com> | 2022-01-31 17:58:35 -0800 |
---|---|---|
committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2022-02-14 21:15:54 -0300 |
commit | 34cb72efdcba47ab4a8b73d0c8cb8c52f042e67a (patch) | |
tree | 52608972d53b8bc84dcf1c4abb8eb8f176c43168 /tools/perf/pmu-events/arch/x86/broadwellde/other.json | |
parent | 3bad20d7d129c3b3063658a0f83974dfe6dac5c4 (diff) | |
download | linux-34cb72efdcba47ab4a8b73d0c8cb8c52f042e67a.tar.bz2 |
perf vendor events: Update metrics for Broadwell DE
Based on TMA_metrics-full.csv version 4.3 at 01.org:
https://download.01.org/perfmon/
Events are still at version 7:
https://download.01.org/perfmon/BDW-DE
Json files generated by:
https://github.com/intel/event-converter-for-linux-perf
This adds TopdownL1_SMT metrics to bdwde-metrics.json. A discussed in:
https://lore.kernel.org/all/20220129080929.837293-4-irogers@google.com/
The TMA_Metrics-full.csv was modified so that BDW-DE is in the server
column with BDX, the Page_Walks_Utilization and
Page_Walks_Utilization_SMT metrics are then copied from BDW.
Tested:
...
6: Parse event definition strings : Ok
7: Simple expression parser : Ok
...
9: Parse perf pmu format : Ok
10: PMU events :
10.1: PMU event table sanity : Ok
10.2: PMU event map aliases : Ok
10.3: Parsing of PMU event table metrics : Ok
10.4: Parsing of PMU event table metrics with fake PMUs : Ok
...
68: Parse and process metrics : Ok
...
88: perf stat metrics (shadow stat) test : Ok
89: perf all metricgroups test : Ok
90: perf all metrics test : Skip
91: perf all PMU test : Ok
...
90 skips due to a lack of floating point samples, which is
understandable.
Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-4-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/broadwellde/other.json')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/broadwellde/other.json | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/other.json b/tools/perf/pmu-events/arch/x86/broadwellde/other.json index 4475249ea9da..4b360fe96698 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/other.json @@ -1,44 +1,44 @@ [ { - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EdgeDetect": "1", - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", "Counter": "0,1,2,3", - "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0_TRANS", "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", - "UMask": "0x2", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", - "UMask": "0x1", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ]
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