diff options
| author | Srinivasa Rao Mandadapu <srivasam@codeaurora.org> | 2021-06-09 19:00:39 +0530 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-06-14 15:01:05 +0100 |
| commit | c223f41c1a52bfe10f1d3311679b1d1f9813e500 (patch) | |
| tree | a8b8d08a557a2611a1b81a5946851d97a02978d0 /sound/soc/qcom/lpass-cpu.c | |
| parent | 08c56cab302a059c1f3a95c164def7b21c67ad2e (diff) | |
| download | linux-c223f41c1a52bfe10f1d3311679b1d1f9813e500.tar.bz2 | |
ASoC: qcom: Add four speaker support on MI2S secondary
Add four speaker support on MI2S secondary block
by using I2S SD1 line on gpio52 pin, and add channel map
control support in the lpass-cpu audio driver.
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20210609133039.4648-1-srivasam@codeaurora.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/qcom/lpass-cpu.c')
| -rw-r--r-- | sound/soc/qcom/lpass-cpu.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/sound/soc/qcom/lpass-cpu.c b/sound/soc/qcom/lpass-cpu.c index 28c7497344e3..98f93240fb2a 100644 --- a/sound/soc/qcom/lpass-cpu.c +++ b/sound/soc/qcom/lpass-cpu.c @@ -29,6 +29,15 @@ #define LPASS_CPU_I2S_SD0_1_2_MASK GENMASK(2, 0) #define LPASS_CPU_I2S_SD0_1_2_3_MASK GENMASK(3, 0) +/* + * Channel maps for Quad channel playbacks on MI2S Secondary + */ +static struct snd_pcm_chmap_elem lpass_quad_chmaps[] = { + { .channels = 4, + .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_RL, + SNDRV_CHMAP_FR, SNDRV_CHMAP_RR } }, + { } +}; static int lpass_cpu_init_i2sctl_bitfields(struct device *dev, struct lpaif_i2sctl *i2sctl, struct regmap *map) { @@ -324,6 +333,25 @@ const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = { }; EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops); +int lpass_cpu_pcm_new(struct snd_soc_pcm_runtime *rtd, + struct snd_soc_dai *dai) +{ + int ret; + struct snd_soc_dai_driver *drv = dai->driver; + struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); + + if (drvdata->mi2s_playback_sd_mode[dai->id] == LPAIF_I2SCTL_MODE_QUAD01) { + ret = snd_pcm_add_chmap_ctls(rtd->pcm, SNDRV_PCM_STREAM_PLAYBACK, + lpass_quad_chmaps, drv->playback.channels_max, 0, + NULL); + if (ret < 0) + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(lpass_cpu_pcm_new); + int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai) { struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai); @@ -846,6 +874,11 @@ int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev) PTR_ERR(drvdata->mi2s_bit_clk[dai_id])); return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]); } + if (drvdata->mi2s_playback_sd_mode[dai_id] == + LPAIF_I2SCTL_MODE_QUAD01) { + variant->dai_driver[dai_id].playback.channels_min = 4; + variant->dai_driver[dai_id].playback.channels_max = 4; + } } /* Allocation for i2sctl regmap fields */ |