diff options
| author | Annaliese McDermond <nh6z@nh6z.net> | 2019-03-21 17:58:51 -0700 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-03-25 15:54:42 +0000 |
| commit | 96c3bb00239de4fb5f4ddca42c1f90d6d9b3c697 (patch) | |
| tree | be7582124228f44f48d77314846af74ebc5d3988 /sound/soc/codecs/tlv320aic32x4.h | |
| parent | fbafbf6517274a797e6e6508c18dd8dba5920c89 (diff) | |
| download | linux-96c3bb00239de4fb5f4ddca42c1f90d6d9b3c697.tar.bz2 | |
ASoC: tlv320aic32x4: Dynamically Determine Clocking
The existing code uses a static lookup table to determine the
settings of the various clock devices on board the chip. This is
limiting in a couple of ways. First, this doesn't allow for any
master clock rates other than the three that have been
precalculated. Additionally, new sample rates are difficult to
add to the table. Witness that the chip is capable of 192000 Hz
sampling, but it is not provided by this driver. Last, if the
driver is clocked by something that isn't a crystal, the
upstream clock may not be able to achieve exactly the rate
requested in the driver. This will mean that clocking will be
slightly off for the sampling clock or that it won't work at all.
This patch determines the settings for all of the clocks at
runtime considering the real conditions of the clocks in the
system. The rules for the clocks are in TI's SLAA557 application
guide on pages 37, 51 and 77.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/tlv320aic32x4.h')
| -rw-r--r-- | sound/soc/codecs/tlv320aic32x4.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/sound/soc/codecs/tlv320aic32x4.h b/sound/soc/codecs/tlv320aic32x4.h index 6ede877b00a0..88205bc97198 100644 --- a/sound/soc/codecs/tlv320aic32x4.h +++ b/sound/soc/codecs/tlv320aic32x4.h @@ -211,7 +211,9 @@ int aic32x4_register_clocks(struct device *dev, const char *mclk_name); #define AIC32X4_DIV_MASK GENMASK(6, 0) /* Clock Limits */ +#define AIC32X4_MAX_DOSR_FREQ 6200000 +#define AIC32X4_MIN_DOSR_FREQ 2800000 +#define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000000 #define AIC32X4_MAX_PLL_CLKIN 20000000 - #endif /* _TLV320AIC32X4_H */ |