diff options
| author | John Hsu <KCHSU0@nuvoton.com> | 2016-11-11 11:34:42 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-11-11 15:35:39 +0000 |
| commit | d6d197458b5fc801b2274f5287a4df6ce74b230f (patch) | |
| tree | 11e1e683afc3148b7912b73ad515bc034448fc08 /sound/soc/codecs/nau8825.h | |
| parent | 93dfec758ff2d0292be35cafd239e929a8973b73 (diff) | |
| download | linux-d6d197458b5fc801b2274f5287a4df6ce74b230f.tar.bz2 | |
ASoC: nau8825: AD/DA over sampling rate configuration
Over Sampling Rate (OSR) is defined as CLK_ADC frequency divided by the
audio sample rate (Fs).
OSR = CLK_ADC / FS
The available OSRs are 32, 64, 128 or 256. Note that the OSR and Fs
values must be selected such that the maximum frequency of CLK_ADC
is less than 6.144 MHz. It is recommended to match the relationship
between OSR and clock SRC according to following Table.
ADC_RATE: 00(OSR=32) | CLK_ADC_SRC: 11(CODEC 1/8)
ADC_RATE: 01(OSR=64) | CLK_ADC_SRC: 10(CODEC1/4)
ADC_RATE: 10(OSR=128) | CLK_ADC_SRC: 01(CODEC 1/2)
ADC_RATE: 11(OSR=256) | CLK_ADC_SRC: 00(CODEC CLK)
The over sampling rate about DAC follows the same rule with ADCs.
The driver changes the OSR to 64 value when initiation for better FLL
performance and applies the dynamic SRC change by different OSR.
Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/nau8825.h')
| -rw-r--r-- | sound/soc/codecs/nau8825.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h index 6365c9c3f8d9..167a2aaad256 100644 --- a/sound/soc/codecs/nau8825.h +++ b/sound/soc/codecs/nau8825.h @@ -115,6 +115,10 @@ #define NAU8825_CLK_SRC_MASK (1 << NAU8825_CLK_SRC_SFT) #define NAU8825_CLK_SRC_VCO (1 << NAU8825_CLK_SRC_SFT) #define NAU8825_CLK_SRC_MCLK (0 << NAU8825_CLK_SRC_SFT) +#define NAU8825_CLK_ADC_SRC_SFT 6 +#define NAU8825_CLK_ADC_SRC_MASK (0x3 << NAU8825_CLK_ADC_SRC_SFT) +#define NAU8825_CLK_DAC_SRC_SFT 4 +#define NAU8825_CLK_DAC_SRC_MASK (0x3 << NAU8825_CLK_DAC_SRC_SFT) #define NAU8825_CLK_MCLK_SRC_MASK (0xf << 0) /* FLL1 (0x04) */ |