diff options
| author | Richard Fitzgerald <rf@opensource.cirrus.com> | 2021-08-05 17:11:04 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2021-08-05 20:17:13 +0100 |
| commit | f1040e86f83b0f7d5f45724500a6a441731ff4b7 (patch) | |
| tree | 74021cd97498288e0673e3b8fdadb1087aa13d62 /sound/soc/codecs/cs42l42.h | |
| parent | 8b353bbeae20e2214c9d9d88bcb2fda4ba145d83 (diff) | |
| download | linux-f1040e86f83b0f7d5f45724500a6a441731ff4b7.tar.bz2 | |
ASoC: cs42l42: PLL must be running when changing MCLK_SRC_SEL
Both SCLK and PLL clocks must be running to drive the glitch-free mux
behind MCLK_SRC_SEL and complete the switchover.
This patch moves the writing of MCLK_SRC_SEL to when the PLL is started
and stopped, so that it only transitions while the PLL is running.
The unconditional write MCLK_SRC_SEL=0 in cs42l42_mute_stream() is safe
because if the PLL is not running MCLK_SRC_SEL is already 0.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Fixes: 43fc357199f9 ("ASoC: cs42l42: Set clock source for both ways of stream")
Link: https://lore.kernel.org/r/20210805161111.10410-1-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/cs42l42.h')
| -rw-r--r-- | sound/soc/codecs/cs42l42.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h index 7bf05ff05f74..3dfeaf6611d1 100644 --- a/sound/soc/codecs/cs42l42.h +++ b/sound/soc/codecs/cs42l42.h @@ -775,6 +775,7 @@ struct cs42l42_private { struct gpio_desc *reset_gpio; struct completion pdn_done; struct snd_soc_jack *jack; + int pll_config; int bclk; u32 sclk; u32 srate; |