diff options
| author | Richard Fitzgerald <rf@opensource.cirrus.com> | 2022-03-04 14:40:15 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-03-07 13:14:59 +0000 |
| commit | 71a6254c8b8aa3dcac3a5cb1d1cc2a2d3a840bfb (patch) | |
| tree | 852ddb46b70b9b55f5a6d50d1be32591f54d1d40 /sound/soc/codecs/cs42l42.h | |
| parent | b6b62d942bbc4d926bcf3799ea3bcaeb105fd04f (diff) | |
| download | linux-71a6254c8b8aa3dcac3a5cb1d1cc2a2d3a840bfb.tar.bz2 | |
ASoC: cs42l42: Add warnings about DETECT_MODE and PLL_START
DETECT_MODE and PLL_START must be zero while HP_PDN and ADC_PDN are
both 1. If this condition is broken it can discharge FILT+ and it
can then take up to 1 second for FILT+ to recharge.
There is no workaround required for this, simply avoiding settings
and sequences that would break the requirement. The driver already
meets the requirement.
But it is not obvious from reading the code that this requirement
exists, or what is ensuring it is met. So it would not currently be
obvious to someone changing the code that there is certain special
behaviour that must be maintained.
To avoid accidental breakage in the future:
- Add comments into the register definitions to warn about this so
that anyone changing the code around DETECT_MODE and PLL_START is
aware of this requirement.
- Add a comment where PLL_START is written to 1 to highlight the
requirement and why it is satisfied.
- Add a comment in cs42l42_setup_hs_type_detect() when DETECT_MODE is
initialized.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220304144015.398656-1-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/cs42l42.h')
| -rw-r--r-- | sound/soc/codecs/cs42l42.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h index 244b24d1f5e9..60d3bdf5d7c9 100644 --- a/sound/soc/codecs/cs42l42.h +++ b/sound/soc/codecs/cs42l42.h @@ -491,7 +491,10 @@ #define CS42L42_TS_UNPLUG 0 #define CS42L42_TS_TRANS 1 -/* Page 0x15 Fractional-N PLL Registers */ +/* + * NOTE: PLL_START must be 0 while both ADC_PDN=1 and HP_PDN=1. + * Otherwise it will prevent FILT+ from charging properly. + */ #define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01) #define CS42L42_PLL_START_SHIFT 0 #define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT) @@ -574,6 +577,10 @@ #define CS42L42_TIP_SENSE_CTRL_MASK (3 << \ CS42L42_TIP_SENSE_CTRL_SHIFT) +/* + * NOTE: DETECT_MODE must be 0 while both ADC_PDN=1 and HP_PDN=1. + * Otherwise it will prevent FILT+ from charging properly. + */ #define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74) #define CS42L42_PDN_MIC_LVL_DET_SHIFT 0 #define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT) |