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authorConor Dooley <conor.dooley@microchip.com>2022-08-20 00:14:16 +0100
committerConor Dooley <conor.dooley@microchip.com>2022-08-23 22:15:55 +0100
commite4009c5fa77b4356aa37ce002e9f9952dfd7a615 (patch)
tree796f269f780625814c7937b9f7a94e96d5f5d216 /samples/uhid
parent2b55915d27dcaa35f54bad7925af0a76001079bc (diff)
downloadlinux-e4009c5fa77b4356aa37ce002e9f9952dfd7a615.tar.bz2
riscv: dts: microchip: mpfs: remove pci axi address translation property
An AXI master address translation table property was inadvertently added to the device tree & this was not caught by dtbs_check at the time. Remove the property - it should not be in mpfs.dtsi anyway as it would be more suitable in -fabric.dtsi nor does it actually apply to the version of the reference design we are using for upstream. Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3 Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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