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| author | Gary R Hook <gary.hook@amd.com> | 2017-12-20 09:47:08 -0700 |
|---|---|---|
| committer | Alex Williamson <alex.williamson@redhat.com> | 2017-12-20 09:47:08 -0700 |
| commit | ff18c4e598de13af6503d6adb66f3ad768b6a53e (patch) | |
| tree | 43b81ef7179015b5793c6ffefd936af281ac7b11 /net | |
| parent | f9fc049ef1e05da3e3d2a45d098ec89b89bf687e (diff) | |
| download | linux-ff18c4e598de13af6503d6adb66f3ad768b6a53e.tar.bz2 | |
iommu/amd: Set the device table entry PPR bit for IOMMU V2 devices
The AMD IOMMU specification Rev 3.00 (December 2016) introduces a
new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register
offset 0030h (IOMMU Extended Feature Register).
When EPHSup=1, the IOMMU hardware requires the PPR bit of the
device table entry (DTE) to be set in order to support PPR for a
particular endpoint device.
Please see https://support.amd.com/TechDocs/48882_IOMMU.pdf for
this revision of the AMD IOMMU specification.
Signed-off-by: Gary R Hook <gary.hook@amd.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Diffstat (limited to 'net')
0 files changed, 0 insertions, 0 deletions