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| author | Lang Cheng <chenglang@huawei.com> | 2020-11-26 15:04:11 +0800 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2020-11-27 12:53:59 -0400 |
| commit | f93c39bc95472dae3b5de71da5c005f47ece3148 (patch) | |
| tree | 1e96c30836bdbd834458331b6e73b12fd671be3a /net/tls/tls_sw.c | |
| parent | bfefae9f108dfa62eb9c16c9e97086fddb4ece04 (diff) | |
| download | linux-f93c39bc95472dae3b5de71da5c005f47ece3148.tar.bz2 | |
RDMA/hns: Add support for QP stash
Stash is a mechanism that uses the core information carried by the ARM AXI
bus to access the L3 cache. It can be used to improve the performance by
increasing the hit ratio of L3 cache. QPs need to enable stash by default.
Link: https://lore.kernel.org/r/1606374251-21512-3-git-send-email-liweihang@huawei.com
Signed-off-by: Lang Cheng <chenglang@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'net/tls/tls_sw.c')
0 files changed, 0 insertions, 0 deletions