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| author | Stratos Karafotis <stratosk@semaphore.gr> | 2014-07-18 08:37:24 -0700 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2014-07-21 13:43:18 +0200 |
| commit | 4ab60c3f32c721e46217e762bcd3e55a8f659c04 (patch) | |
| tree | 5edf608225d61bc595e99fe76c5521501dda1624 /net/iucv | |
| parent | c410833a3c96b325c68987c2544becad39079c33 (diff) | |
| download | linux-4ab60c3f32c721e46217e762bcd3e55a8f659c04.tar.bz2 | |
cpufreq: intel_pstate: Disable interrupts during MSRs reading
According to Intel 64 and IA-32 Architectures SDM, Volume 3,
Chapter 14.2, "Software needs to exercise care to avoid delays
between the two RDMSRs (for example interrupts)".
So, disable interrupts during reading MSRs IA32_APERF and IA32_MPERF.
This should increase the accuracy of the calculations.
Signed-off-by: Stratos Karafotis <stratosk@semaphore.gr>
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'net/iucv')
0 files changed, 0 insertions, 0 deletions