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| author | Catalin Marinas <catalin.marinas@arm.com> | 2022-01-28 16:14:06 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2022-01-28 16:14:06 +0000 |
| commit | df20597044e59cd383135b3d91c5b131dc333969 (patch) | |
| tree | 784072ce56298e53c62aebba5c4656812475949d /lib/sha1.c | |
| parent | 9ae279ecabe3e5bb85567e6c7371f4d35cfa00d6 (diff) | |
| parent | 708e8af4924ec2fdd5b81fe09192c6bac2f86935 (diff) | |
| download | linux-df20597044e59cd383135b3d91c5b131dc333969.tar.bz2 | |
Merge tag 'trbe-cortex-a510-errata' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux into for-next/fixes
coresight: trbe: Workaround Cortex-A510 erratas
This pull request is providing arm64 definitions to support
TRBE Cortex-A510 erratas.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
* tag 'trbe-cortex-a510-errata' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux:
arm64: errata: Add detection for TRBE trace data corruption
arm64: errata: Add detection for TRBE invalid prohibited states
arm64: errata: Add detection for TRBE ignored system register writes
arm64: Add Cortex-A510 CPU part definition
Diffstat (limited to 'lib/sha1.c')
0 files changed, 0 insertions, 0 deletions