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author | Andrew Lunn <andrew@lunn.ch> | 2012-10-27 15:28:58 +0200 |
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committer | Linus Walleij <linus.walleij@linaro.org> | 2012-10-30 22:34:20 +0100 |
commit | 8fcff5f13773aa3898df1d13a1615d468079cb15 (patch) | |
tree | 6ac1aac693b076871edfa4855635b66bde74a832 /ipc/ipc_sysctl.c | |
parent | c9c55d9211150b589d2d39a45cf5f96c70a51a47 (diff) | |
download | linux-8fcff5f13773aa3898df1d13a1615d468079cb15.tar.bz2 |
GPIO: mvebu-gpio: Don't initialize the mask_cache
Due to the SMP nature of some of the chips, which have per CPU
registers, the driver does not use the generic irq_gc_mask_set_bit() &
irq_gc_mask_clr_bit() functions, which only support a single register.
The driver has its own implementation of these functions, which can
pick the correct register depending on the CPU being used. The
functions do however use the gc->mask_cache value.
The call to irq_setup_generic_chip() was passing
IRQ_GC_INIT_MASK_CACHE, which caused the gc->mask_cache to be
initialized to the contents of some random register. This resulted in
unexpected interrupts been delivered from random GPIO lines.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jamie Lentin <jm@lentin.co.uk>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'ipc/ipc_sysctl.c')
0 files changed, 0 insertions, 0 deletions