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| author | Vinod Koul <vinod.koul@intel.com> | 2017-02-21 21:13:57 +0530 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2017-02-21 21:13:57 +0530 |
| commit | e4e48c47d15df1dd5f74d3b5e8fc4c7817f45133 (patch) | |
| tree | 6eec89260467cb62b721550575bcda2acff68b75 /include | |
| parent | b802c8410ca915e7772e738e68420115f1a3c811 (diff) | |
| parent | f7c799e950f96191a16f18606e43e6f861b2a361 (diff) | |
| download | linux-e4e48c47d15df1dd5f74d3b5e8fc4c7817f45133.tar.bz2 | |
Merge branch 'topic/intel' into for-linus
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/dma/dw.h | 2 | ||||
| -rw-r--r-- | include/linux/platform_data/dma-dw.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/dma/dw.h b/include/linux/dma/dw.h index ccfd0c3777df..b63b25814d77 100644 --- a/include/linux/dma/dw.h +++ b/include/linux/dma/dw.h @@ -23,6 +23,7 @@ struct dw_dma; /** * struct dw_dma_chip - representation of DesignWare DMA controller hardware * @dev: struct device of the DMA controller + * @id: instance ID * @irq: irq line * @regs: memory mapped I/O space * @clk: hclk clock @@ -31,6 +32,7 @@ struct dw_dma; */ struct dw_dma_chip { struct device *dev; + int id; int irq; void __iomem *regs; struct clk *clk; diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h index e69e415d0d98..896cb71a382c 100644 --- a/include/linux/platform_data/dma-dw.h +++ b/include/linux/platform_data/dma-dw.h @@ -41,6 +41,7 @@ struct dw_dma_slave { * @is_private: The device channels should be marked as private and not for * by the general purpose DMA channel allocator. * @is_memcpy: The device channels do support memory-to-memory transfers. + * @is_idma32: The type of the DMA controller is iDMA32 * @chan_allocation_order: Allocate channels starting from 0 or 7 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. * @block_size: Maximum block size supported by the controller @@ -53,6 +54,7 @@ struct dw_dma_platform_data { unsigned int nr_channels; bool is_private; bool is_memcpy; + bool is_idma32; #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ unsigned char chan_allocation_order; |