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| author | Kees Cook <keescook@chromium.org> | 2020-06-08 20:15:09 -0700 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2020-06-18 11:41:32 +0200 |
| commit | a13b9d0b97211579ea63b96c606de79b963c0f47 (patch) | |
| tree | 6cc00b548d67524d637c808aeb2d74fea61d8f4c /include | |
| parent | cc5277fe66cf3ad68f41f1c539b2ef0d5e432974 (diff) | |
| download | linux-a13b9d0b97211579ea63b96c606de79b963c0f47.tar.bz2 | |
x86/cpu: Use pinning mask for CR4 bits needing to be 0
The X86_CR4_FSGSBASE bit of CR4 should not change after boot[1]. Older
kernels should enforce this bit to zero, and newer kernels need to
enforce it depending on boot-time configuration (e.g. "nofsgsbase").
To support a pinned bit being either 1 or 0, use an explicit mask in
combination with the expected pinned bit values.
[1] https://lore.kernel.org/lkml/20200527103147.GI325280@hirez.programming.kicks-ass.net
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/202006082013.71E29A42@keescook
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions