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authorSowjanya Komatineni <skomatineni@nvidia.com>2019-04-15 14:30:27 -0700
committerMark Brown <broonie@kernel.org>2019-05-02 10:37:55 +0900
commit937e6d756422637eeb212c645ded69569a67fabc (patch)
tree64f02caa4a8d990d28d4cffd9b47b9fd3546dc3d /include
parentbf6e839657598b77e40eb18225f8660c4778cb19 (diff)
downloadlinux-937e6d756422637eeb212c645ded69569a67fabc.tar.bz2
spi: expand mode support
This patch changes mode and mode_bits from u16 to u32 to allow more mode configurations. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include')
-rw-r--r--include/linux/spi/spi.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 589f9dc9ac2b..053abd22ad31 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -143,7 +143,7 @@ struct spi_device {
u32 max_speed_hz;
u8 chip_select;
u8 bits_per_word;
- u16 mode;
+ u32 mode;
#define SPI_CPHA 0x01 /* clock phase */
#define SPI_CPOL 0x02 /* clock polarity */
#define SPI_MODE_0 (0|0) /* (original MicroWire) */
@@ -443,7 +443,7 @@ struct spi_controller {
u16 dma_alignment;
/* spi_device.mode flags understood by this controller driver */
- u16 mode_bits;
+ u32 mode_bits;
/* bitmask of supported bits_per_word for transfers */
u32 bits_per_word_mask;
@@ -1291,7 +1291,7 @@ struct spi_board_info {
/* mode becomes spi_device.mode, and is essential for chips
* where the default of SPI_CS_HIGH = 0 is wrong.
*/
- u16 mode;
+ u32 mode;
/* ... may need additional spi_device chip config data here.
* avoid stuff protocol drivers can set; but include stuff