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authorJason Gunthorpe <jgg@nvidia.com>2021-06-22 15:08:39 -0300
committerJason Gunthorpe <jgg@nvidia.com>2021-06-22 15:08:39 -0300
commit2833c977c3049f521784e8954d4c90e4941187db (patch)
tree3525a0d9c208577b852a460052290c3afa3406ef /include
parentfdcebbc2ac2cfd82a18857b0c85067fa7e8f5233 (diff)
parent336529518e9724d4cecabc622e57bcdce02e7c61 (diff)
downloadlinux-2833c977c3049f521784e8954d4c90e4941187db.tar.bz2
Merge branch 'mlx5_realtime_ts' into rdma.git for-next
Aharon Landau says: ==================== In case device supports only real-time timestamp, the kernel will fail to create QP despite rdma-core requested such timestamp type. It is because device returns free-running timestamp, and the conversion from free-running to real-time is performed in the user space. This series fixes it, by returning real-time timestamp. ==================== * mlx5_realtime_ts: RDMA/mlx5: Support real-time timestamp directly from the device RDMA/mlx5: Refactor get_ts_format functions to simplify code Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mlx5/mlx5_ifc.h36
-rw-r--r--include/linux/mlx5/qp.h4
-rw-r--r--include/uapi/rdma/mlx5-abi.h2
3 files changed, 10 insertions, 32 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index eb86e80e4643..668e1d016066 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -953,9 +953,9 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
};
enum {
- MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
- MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
- MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
+ MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
+ MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
+ MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
};
struct mlx5_ifc_roce_cap_bits {
@@ -1296,18 +1296,6 @@ enum {
MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
};
-enum {
- MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
- MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
- MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
-};
-
-enum {
- MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
- MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
- MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
-};
-
struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_0[0x1f];
u8 vhca_resource_manager[0x1];
@@ -2944,9 +2932,9 @@ enum {
};
enum {
- MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
- MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
- MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
+ MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
+ MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
+ MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
};
struct mlx5_ifc_qpc_bits {
@@ -3396,12 +3384,6 @@ enum {
MLX5_SQC_STATE_ERR = 0x3,
};
-enum {
- MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
- MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
- MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
-};
-
struct mlx5_ifc_sqc_bits {
u8 rlky[0x1];
u8 cd_master[0x1];
@@ -3507,12 +3489,6 @@ enum {
MLX5_RQC_STATE_ERR = 0x3,
};
-enum {
- MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
- MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
- MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
-};
-
struct mlx5_ifc_rqc_bits {
u8 rlky[0x1];
u8 delay_drop_en[0x1];
diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
index b7deb790f257..61e48d459b23 100644
--- a/include/linux/mlx5/qp.h
+++ b/include/linux/mlx5/qp.h
@@ -550,8 +550,8 @@ static inline const char *mlx5_qp_state_str(int state)
static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
{
return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
- MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
- MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
+ MLX5_TIMESTAMP_FORMAT_FREE_RUNNING :
+ MLX5_TIMESTAMP_FORMAT_DEFAULT;
}
#endif /* MLX5_QP_H */
diff --git a/include/uapi/rdma/mlx5-abi.h b/include/uapi/rdma/mlx5-abi.h
index 995faf8f44bd..8597e6f22a1c 100644
--- a/include/uapi/rdma/mlx5-abi.h
+++ b/include/uapi/rdma/mlx5-abi.h
@@ -102,6 +102,7 @@ enum mlx5_ib_alloc_ucontext_resp_mask {
MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2,
MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3,
+ MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS = 1UL << 4,
};
enum mlx5_user_cmds_supp_uhw {
@@ -271,6 +272,7 @@ struct mlx5_ib_query_device_resp {
enum mlx5_ib_create_cq_flags {
MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1,
+ MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS = 1 << 2,
};
struct mlx5_ib_create_cq {