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| author | Dan Williams <dan.j.williams@intel.com> | 2022-11-29 10:48:48 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-03 13:40:17 -0800 |
| commit | bd09626b39dff97779e1543e25e60ab2876e7e88 (patch) | |
| tree | 42ddd99d1cf5e1a99be5eff8186f746a54d5032e /include/trace | |
| parent | a1554e9cac5ea04aaf2fb2de0df9936a94cb96fc (diff) | |
| download | linux-bd09626b39dff97779e1543e25e60ab2876e7e88.tar.bz2 | |
cxl/pci: Find and map the RAS Capability Structure
The RAS Capability Structure has some ancillary information that may be
relevant with respect to AER events, link and protcol error status
registers. Map the RAS Capability Registers in support of defining a
'struct pci_error_handlers' instance for the cxl_pci driver.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/166974412803.1608150.7096566580400947001.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include/trace')
0 files changed, 0 insertions, 0 deletions