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| author | Arnd Bergmann <arnd@arndb.de> | 2022-02-28 15:10:35 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2022-02-28 15:10:36 +0100 |
| commit | cba4cdeb35a2840fd3093d023137057c890de898 (patch) | |
| tree | 0dbd41d6b0fa2673b0789533730aa9015dc3af9c /include/dt-bindings/power | |
| parent | 877d1d8112ae018defb862884503af88a583e79d (diff) | |
| parent | a4ad66da3fccebdcbd53d55c035d5851b73f8bcb (diff) | |
| download | linux-cba4cdeb35a2840fd3093d023137057c890de898.tar.bz2 | |
Merge tag 'tegra-for-5.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
dt-bindings: Changes for v5.18-rc1
This contains additions to various DT bindings includes (such as clocks,
resets, power domains, memory controller clients and SMMU stream IDs)
for Tegra234.
* tag 'tegra-for-5.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: memory: Add Tegra234 PCIe memory
dt-bindings: power: Add Tegra234 PCIe power domains
dt-bindings: Add Tegra234 PCIe clocks and resets
dt-bindings: Document Tegra234 HDA support
dt-bindings: Add HDA support for Tegra234
dt-bindings: Add Tegra234 APE support
dt-bindings: Add headers for Tegra234 PWM
dt-bindings: Add headers for Tegra234 I2C
Link: https://lore.kernel.org/r/20220225164741.1064416-2-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include/dt-bindings/power')
| -rw-r--r-- | include/dt-bindings/power/tegra234-powergate.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h new file mode 100644 index 000000000000..f610eee9bce8 --- /dev/null +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T234_POWERGATE_T234_H_ +#define __ABI_MACH_T234_POWERGATE_T234_H_ + +#define TEGRA234_POWER_DOMAIN_AUD 2U +#define TEGRA234_POWER_DOMAIN_DISP 3U +#define TEGRA234_POWER_DOMAIN_PCIEX8A 5U +#define TEGRA234_POWER_DOMAIN_PCIEX4A 6U +#define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U +#define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U +#define TEGRA234_POWER_DOMAIN_PCIEX1A 9U +#define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U +#define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U +#define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U +#define TEGRA234_POWER_DOMAIN_PCIEX8B 16U +#define TEGRA234_POWER_DOMAIN_MGBEA 17U +#define TEGRA234_POWER_DOMAIN_MGBEB 18U +#define TEGRA234_POWER_DOMAIN_MGBEC 19U + +#endif |