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| author | Tomasz Figa <t.figa@samsung.com> | 2014-06-30 15:06:43 +0200 |
|---|---|---|
| committer | Tomasz Figa <t.figa@samsung.com> | 2014-06-30 15:06:43 +0200 |
| commit | bdfcdf18c380a3c376b42709a89eb2cc52e95ae0 (patch) | |
| tree | c6a93004468a92c606bf0dd435bdbfa6f10bc49b /include/dt-bindings/clock/exynos5420.h | |
| parent | 27b8d5f723e64b5f7beac45a4d5785906d0a2f9d (diff) | |
| parent | 44ff0254b89079a8a95e652635e760d93196ac1f (diff) | |
| download | linux-bdfcdf18c380a3c376b42709a89eb2cc52e95ae0.tar.bz2 | |
Merge branch 'v3.16-samsung-clk-fixes-1' into samsung-clk-next
Diffstat (limited to 'include/dt-bindings/clock/exynos5420.h')
| -rw-r--r-- | include/dt-bindings/clock/exynos5420.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 97dcb89d37d3..14e1c8f9640c 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -63,7 +63,6 @@ #define CLK_SCLK_MPHY_IXTAL24 161 /* gate clocks */ -#define CLK_ACLK66_PERIC 256 #define CLK_UART0 257 #define CLK_UART1 258 #define CLK_UART2 259 |