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authorNathan Rossi <nathan.rossi@digi.com>2022-04-22 04:35:32 +0000
committerMarc Zyngier <maz@kernel.org>2022-05-04 16:40:06 +0100
commit8ca61cde32c1db778aa52631184484e051cbdf27 (patch)
tree171014b1ae1258a2a117e57ed00a0885bef79225 /fs
parentf03a9670d27d23fe734a456f16e2579b21ec02b4 (diff)
downloadlinux-8ca61cde32c1db778aa52631184484e051cbdf27.tar.bz2
irqchip/armada-370-xp: Enable MSI affinity configuration
With multiple devices attached via PCIe to an Armada 385 it is possible to overwhelm a single CPU with MSI interrupts. Under certain scenarios configuring the interrupts to be handled by more than one CPU would prevent the system from being overwhelmed. However the irqchip-aramada-370-xp driver is configured to only handle MSIs on the boot CPU, and provides no affinity configuration. This change adds support to the armada-370-xp driver to allow for configuring the affinity of specific MSI irqs and to generate the interrupts on secondary CPUs. This is done by enabling the private doorbell for all online CPUs and configures all CPUs to unmask MSI specific private doorbell bits. The CPU affinity selection of the interrupt is handled by the target list of the software triggered interrupt value, which is provided as the MSI message. The message has the associated CPU bit set for the target CPU. For private doorbell interrupts only one bit can be set otherwise all CPUs will receive the interrupt, so the lowest CPU in the affinity mask is used. This means that by default the first CPU will handle all the interrupts as was the case before. Signed-off-by: Nathan Rossi <nathan.rossi@digi.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220422043532.146946-1-nathan@nathanrossi.com
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