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authorStephen Boyd <sboyd@kernel.org>2019-04-19 13:11:39 -0700
committerStephen Boyd <sboyd@kernel.org>2019-04-19 13:11:39 -0700
commit93737fe93ec6cd3ffe49f631ad854c36a3d78ac2 (patch)
treee4f65c542420799e6cbce22297c5f05008b1ccdf /fs/ceph/locks.c
parent9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff)
parentc77cebac96a9edf1f3a508b475110f5d44196901 (diff)
downloadlinux-93737fe93ec6cd3ffe49f631ad854c36a3d78ac2.tar.bz2
Merge tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Maxime Ripard: Our usual bunch of changes, this time, it's mainly: - Export a new clock for the MBUS controller on the A13 - H6 fixes to support a finer clocking of the video and VPU engines - Add some Kconfig options - Some bit offset fixes * tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun5i: Export the MBUS clock clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate clk: sunxi-ng: h6: Preset hdmi-cec clock parent clk: sunxi: Add Kconfig options clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset clk: sunxi-ng: Allow DE clock to set parent rate
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