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author | Paul Burton <paul.burton@imgtec.com> | 2017-08-12 19:49:29 -0700 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2017-08-30 00:57:26 +0200 |
commit | 829ca2be9c55c786d404a5129ed88a2899fe07af (patch) | |
tree | 3127640238550c144a90c1edbdf6e48f0030cd03 /firmware | |
parent | 2c981e325f0c18e24ce252f16f5018b9ee805212 (diff) | |
download | linux-829ca2be9c55c786d404a5129ed88a2899fe07af.tar.bz2 |
MIPS: CPC: Use BIT/GENMASK for register fields, order & drop shifts
Tidy up asm/mips-cpc.h in a similar way to what "MIPS: CM: Use
BIT/GENMASK for register fields, order & drop shifts" did for
asm/mips-cm.h.
We use BIT() & GENMASK() to simplify the definition of register fields,
drop the _SHF definitions since that information can be found in the
_MSK ones, and then drop the _MSK suffix.
Fields definitions are moved to be next to the appropriate register
definition, making it easier to link the two & keep everything ordered
by register address. Comments are added including the name of each
register & a brief description of its purpose which helps to understand
what registers are for, link them back to hardware documentation or grep
for them.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/17003/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'firmware')
0 files changed, 0 insertions, 0 deletions