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authorWolfram Sang <wsa+renesas@sang-engineering.com>2016-03-02 23:33:34 +0100
committerThierry Reding <thierry.reding@gmail.com>2016-03-23 17:11:02 +0100
commitbea307c16a3a297f87c7ab9a54de686da2afbad5 (patch)
treed97b9c88778598de9928795b860270634bce8792 /drivers
parent92e963f50fc74041b5e9e744c330dca48e04f08d (diff)
downloadlinux-bea307c16a3a297f87c7ab9a54de686da2afbad5.tar.bz2
pwm: img: Test clock rate to avoid division by 0
The clk API may return 0 on clk_get_rate(), so we should check the result before using it as a divisor. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pwm/pwm-img.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/pwm/pwm-img.c b/drivers/pwm/pwm-img.c
index 8a029f9bc18c..2fb30deee345 100644
--- a/drivers/pwm/pwm-img.c
+++ b/drivers/pwm/pwm-img.c
@@ -237,6 +237,11 @@ static int img_pwm_probe(struct platform_device *pdev)
}
clk_rate = clk_get_rate(pwm->pwm_clk);
+ if (!clk_rate) {
+ dev_err(&pdev->dev, "pwm clock has no frequency\n");
+ ret = -EINVAL;
+ goto disable_pwmclk;
+ }
/* The maximum input clock divider is 512 */
val = (u64)NSEC_PER_SEC * 512 * pwm->data->max_timebase;