diff options
| author | Alvin Lee <alvin.lee2@amd.com> | 2019-12-30 14:29:06 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-01-16 14:16:27 -0500 |
| commit | 9f21f3792ffb669623cbad8b084f75aa49c98786 (patch) | |
| tree | 5e47cc9fcaf3e43747b39eb4a38d28ec4bd1d510 /drivers | |
| parent | 8547058b17f1f4fba10f389191dd7e08bf95b791 (diff) | |
| download | linux-9f21f3792ffb669623cbad8b084f75aa49c98786.tar.bz2 | |
drm/amd/display: Enable double buffer for OTG_BLANK
[Why]
Currently if seamless boot is enabled, we will skip double buffer enable
for OTG_BLANK. However, we need the double buffer enable in order to
block global sync signals when OTG becomes blanked (for PSR). Blocking
global sync signals prevent pipe from requesting data.
[How]
Move tg_init before seamless boot check.
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 5347a85f10d7..f2127afb37b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1188,8 +1188,14 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context) if (can_apply_seamless_boot && pipe_ctx->stream != NULL && pipe_ctx->stream_res.tg->funcs->is_tg_enabled( - pipe_ctx->stream_res.tg)) + pipe_ctx->stream_res.tg)) { + // Enable double buffering for OTG_BLANK no matter if + // seamless boot is enabled or not to suppress global sync + // signals when OTG blanked. This is to prevent pipe from + // requesting data while in PSR. + tg->funcs->tg_init(tg); continue; + } /* Disable on the current state so the new one isn't cleared. */ pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; |