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author | José Roberto de Souza <jose.souza@intel.com> | 2021-11-19 06:09:31 -0800 |
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committer | José Roberto de Souza <jose.souza@intel.com> | 2021-12-01 11:08:12 -0800 |
commit | 96b1c450b386b34479c0d6c5e24ebee84261433a (patch) | |
tree | 6b5d8db8d6385910b75d7e664cda0d9d235caee7 /drivers | |
parent | f3799ff16fcfacd44aee55db162830df461b631f (diff) | |
download | linux-96b1c450b386b34479c0d6c5e24ebee84261433a.tar.bz2 |
drm/i915: Add workaround numbers to GEN7_COMMON_SLICE_CHICKEN1 whitelisting
Those two workarounds needs to be implemented in UMD, KMD only needs
to whitelist the registers, so here only adding the workaround number
to facilitate future workaroud table checks.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211119140931.32791-2-jose.souza@intel.com
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index cd2935b9e7c8..c3211325c2d3 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1869,7 +1869,11 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) RING_FORCE_TO_NONPRIV_ACCESS_RD | RING_FORCE_TO_NONPRIV_RANGE_4); - /* Wa_1808121037:tgl */ + /* + * Wa_1808121037:tgl + * Wa_14012131227:dg1 + * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p + */ whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); /* Wa_1806527549:tgl */ |