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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-09-21 21:12:45 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-09-24 15:54:29 +0300 |
| commit | 5f524aea39d9e2a74c063f340a77516e454badce (patch) | |
| tree | 57e660b76ac781d99331bdb72b813bf1bae99506 /drivers | |
| parent | 2f051f6774bb8c6807b2287e6ca482089bd92364 (diff) | |
| download | linux-5f524aea39d9e2a74c063f340a77516e454badce.tar.bz2 | |
drm/i915/fbc: Implement Wa_16011863758 for icl+
There's some kind of weird corner cases in FBC which requires
FBC segments to be separated by at least one extra cacheline.
Make sure that is present.
v2: Respin to fit in with skl_fbc_min_cfb_stride()
v3: Make it build
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210921181245.15091-1-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fbc.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index eeb97305e767..37ebed8d228d 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -84,7 +84,8 @@ static unsigned int _intel_fbc_cfb_stride(const struct intel_fbc_state_cache *ca } /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */ -static unsigned int skl_fbc_min_cfb_stride(const struct intel_fbc_state_cache *cache) +static unsigned int skl_fbc_min_cfb_stride(struct drm_i915_private *i915, + const struct intel_fbc_state_cache *cache) { unsigned int limit = 4; /* 1:4 compression limit is the worst case */ unsigned int cpp = 4; /* FBC always 4 bytes per pixel */ @@ -95,6 +96,13 @@ static unsigned int skl_fbc_min_cfb_stride(const struct intel_fbc_state_cache *c stride = cache->plane.src_w * cpp * height / limit; /* + * Wa_16011863758: icl+ + * Avoid some hardware segment address miscalculation. + */ + if (DISPLAY_VER(i915) >= 11) + stride += 64; + + /* * At least some of the platforms require each 4 line segment to * be 512 byte aligned. Just do it always for simplicity. */ @@ -116,7 +124,7 @@ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915, * that regardless of the compression limit we choose later. */ if (DISPLAY_VER(i915) >= 9) - return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(cache)); + return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(i915, cache)); else return stride; } |