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authorAndrew Bresticker <abrestic@chromium.org>2014-09-18 14:47:26 -0700
committerRalf Baechle <ralf@linux-mips.org>2014-11-24 07:44:56 +0100
commit4a6a3ea392306b04fc687d4314efba562121cc9a (patch)
tree108812971050e86179140b7754d335b54b134509 /drivers
parentfbd552417bf275f6da591a0118a019b3006245fd (diff)
downloadlinux-4a6a3ea392306b04fc687d4314efba562121cc9a.tar.bz2
irqchip: mips-gic: Use separate edge/level irq_chips
GIC edge-triggered interrupts must be acknowledged by clearing the edge detector via a write to GIC_SH_WEDGE. Create a separate edge-triggered irq_chip with the appropriate irq_ack() callback. This also allows us to get rid of gic_irq_flags. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7818/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/irqchip/irq-mips-gic.c32
1 files changed, 21 insertions, 11 deletions
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 3cd91d34973d..64d7d571df62 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -24,7 +24,6 @@
unsigned int gic_frequency;
unsigned int gic_present;
unsigned long _gic_base;
-unsigned int gic_irq_flags[GIC_NUM_INTRS];
unsigned int gic_cpu_pin;
struct gic_pcpu_mask {
@@ -45,6 +44,7 @@ static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
static DEFINE_SPINLOCK(gic_lock);
static struct irq_domain *gic_irq_domain;
static int gic_shared_intrs;
+static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
static void __gic_irq_dispatch(void);
@@ -229,9 +229,7 @@ static void gic_ack_irq(struct irq_data *d)
{
unsigned int irq = d->hwirq;
- /* Clear edge detector */
- if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
- GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
+ GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
}
static int gic_set_type(struct irq_data *d, unsigned int type)
@@ -276,11 +274,13 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
}
if (is_edge) {
- gic_irq_flags[irq] |= GIC_TRIG_EDGE;
- __irq_set_handler_locked(d->irq, handle_edge_irq);
+ __irq_set_chip_handler_name_locked(d->irq,
+ &gic_edge_irq_controller,
+ handle_edge_irq, NULL);
} else {
- gic_irq_flags[irq] &= ~GIC_TRIG_EDGE;
- __irq_set_handler_locked(d->irq, handle_level_irq);
+ __irq_set_chip_handler_name_locked(d->irq,
+ &gic_level_irq_controller,
+ handle_level_irq, NULL);
}
spin_unlock_irqrestore(&gic_lock, flags);
@@ -318,7 +318,17 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
}
#endif
-static struct irq_chip gic_irq_controller = {
+static struct irq_chip gic_level_irq_controller = {
+ .name = "MIPS GIC",
+ .irq_mask = gic_mask_irq,
+ .irq_unmask = gic_unmask_irq,
+ .irq_set_type = gic_set_type,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = gic_set_affinity,
+#endif
+};
+
+static struct irq_chip gic_edge_irq_controller = {
.name = "MIPS GIC",
.irq_ack = gic_ack_irq,
.irq_mask = gic_mask_irq,
@@ -431,7 +441,6 @@ static void __init gic_basic_init(int numvpes)
GIC_SET_POLARITY(i, GIC_POL_POS);
GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
GIC_CLR_INTR_MASK(i);
- gic_irq_flags[i] = 0;
}
vpe_local_setup(numvpes);
@@ -442,7 +451,8 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
{
unsigned long flags;
- irq_set_chip_and_handler(virq, &gic_irq_controller, handle_level_irq);
+ irq_set_chip_and_handler(virq, &gic_level_irq_controller,
+ handle_level_irq);
spin_lock_irqsave(&gic_lock, flags);
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(hw)),