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authorLinus Torvalds <torvalds@linux-foundation.org>2014-07-13 12:10:18 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2014-07-13 12:10:18 -0700
commit2f3870e9e8600cd34030e622fea4bc236f855c24 (patch)
tree1b1ec6e5dc28cad6a2727acf06fdfec6fcdea7a8 /drivers
parent5fa77b54eff1e4fb38494b5a24c66768d6e7c148 (diff)
parentcacadb4ff969a82628d47db87b5a531be466b134 (diff)
downloadlinux-2f3870e9e8600cd34030e622fea4bc236f855c24.tar.bz2
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "This week's arm-soc fixes: - Another set of OMAP fixes * Clock fixes * Restart handling * PHY regulators * SATA hwmod data for DRA7 + Some trivial fixes and removal of a bit of dead code - Exynos fixes * A bunch of clock fixes * Some SMP fixes * Exynos multi-core timer: register as clocksource and fix ftrace. + a few other minor fixes There's also a couple more patches, and at91 fix for USB caused by common clock conversion, and more MAINTAINERS entries for shmobile. We're definitely switching to only regression fixes from here on out, we've been a little less strict than usual up until now" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits) ARM: at91: at91sam9x5: add clocks for usb device ARM: EXYNOS: Register cpuidle device only on exynos4210 and 5250 ARM: dts: Add clock property for mfc_pd in exynos5420 clk: exynos5420: Add IDs for clocks used in PD mfc ARM: EXYNOS: Add support for clock handling in power domain ARM: OMAP2+: Remove non working OMAP HDMI audio initialization ARM: imx: fix shared gate clock ARM: dts: Update the parent for Audss clocks in Exynos5420 ARM: EXYNOS: Update secondary boot addr for secure mode ARM: dts: Fix TI CPSW Phy mode selection on IGEP COM AQUILA. ARM: dts: am335x-evmsk: Enable the McASP FIFO for audio ARM: dts: am335x-evm: Enable the McASP FIFO for audio ARM: OMAP2+: Make GPMC skip disabled devices ARM: OMAP2+: create dsp device only on OMAP3 SoCs ARM: dts: dra7-evm: Make VDDA_1V8_PHY supply always on ARM: DRA7/AM43XX: fix header definition for omap44xx_restart ARM: OMAP2+: clock/dpll: fix _dpll_test_fint arithmetics overflow ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss ARM: DRA7: hwmod: Fixup SATA hwmod ARM: OMAP3: PRM/CM: Add back macros used by TI DSP/Bridge driver ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c6
-rw-r--r--drivers/clocksource/exynos_mct.c20
2 files changed, 22 insertions, 4 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9d7d7eed03fd..f74f882f7f29 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -631,7 +631,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
SRC_TOP4, 16, 1),
MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
- MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
+ MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
+ SRC_TOP4, 28, 1),
MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
SRC_TOP5, 0, 1),
@@ -684,7 +685,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
SRC_TOP11, 12, 1),
MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
- MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
+ MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
+ SRC_TOP11, 28, 1),
MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
SRC_TOP12, 4, 1),
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index f71d55f5e6e5..ab51bf20a3ed 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -162,7 +162,7 @@ static void exynos4_mct_frc_start(void)
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}
-static cycle_t exynos4_frc_read(struct clocksource *cs)
+static cycle_t notrace _exynos4_frc_read(void)
{
unsigned int lo, hi;
u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
@@ -176,6 +176,11 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
return ((cycle_t)hi << 32) | lo;
}
+static cycle_t exynos4_frc_read(struct clocksource *cs)
+{
+ return _exynos4_frc_read();
+}
+
static void exynos4_frc_resume(struct clocksource *cs)
{
exynos4_mct_frc_start();
@@ -192,13 +197,24 @@ struct clocksource mct_frc = {
static u64 notrace exynos4_read_sched_clock(void)
{
- return exynos4_frc_read(&mct_frc);
+ return _exynos4_frc_read();
+}
+
+static struct delay_timer exynos4_delay_timer;
+
+static cycles_t exynos4_read_current_timer(void)
+{
+ return _exynos4_frc_read();
}
static void __init exynos4_clocksource_init(void)
{
exynos4_mct_frc_start();
+ exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
+ exynos4_delay_timer.freq = clk_rate;
+ register_current_timer_delay(&exynos4_delay_timer);
+
if (clocksource_register_hz(&mct_frc, clk_rate))
panic("%s: can't register clocksource\n", mct_frc.name);