diff options
| author | Yunsheng Lin <linyunsheng@huawei.com> | 2019-04-15 21:48:39 +0800 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-04-15 13:39:19 -0700 |
| commit | 2566f10676ba996b745e138f54f3e2f974311692 (patch) | |
| tree | cc6617d85b04cafc9435ad000d1c606c36dde0fa /drivers | |
| parent | 8a9a654b5b5233e7459abcc5f65c53df14b33f67 (diff) | |
| download | linux-2566f10676ba996b745e138f54f3e2f974311692.tar.bz2 | |
net: hns3: fix for vport->bw_limit overflow problem
When setting vport->bw_limit to hdev->tm_info.pg_info[0].bw_limit
in hclge_tm_vport_tc_info_update, vport->bw_limit can be as big as
HCLGE_ETHER_MAX_RATE (100000), which can not fit into u16 (65535).
So this patch fixes it by using u32 for vport->bw_limit.
Fixes: 848440544b41 ("net: hns3: Add support of TX Scheduler & Shaper to HNS3 driver")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index f04a52f143ae..e736030ac180 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -854,7 +854,7 @@ struct hclge_vport { u16 alloc_rss_size; u16 qs_offset; - u16 bw_limit; /* VSI BW Limit (0 = disabled) */ + u32 bw_limit; /* VSI BW Limit (0 = disabled) */ u8 dwrr; struct hclge_port_base_vlan_config port_base_vlan_cfg; |