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| author | Jiapeng Chong <jiapeng.chong@linux.alibaba.com> | 2022-05-10 14:04:40 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-05-13 13:14:37 -0400 |
| commit | 0a360aeb861e94a9d17cb7e63887ef7876bac1df (patch) | |
| tree | cfe5415f838416a506d82b260b12ee17006a6ff4 /drivers | |
| parent | 81c5495910e81c2cadcb9118ca0c8803ab3bde61 (diff) | |
| download | linux-0a360aeb861e94a9d17cb7e63887ef7876bac1df.tar.bz2 | |
drm/amdgpu: clean up some inconsistent indenting
Eliminate the follow smatch warning:
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c:35 nbio_v7_7_get_rev_id() warn:
inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c:214 nbio_v7_7_init_registers()
warn: inconsistent indenting.
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c index e32c874b42b5..cdc0c9779848 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c @@ -32,8 +32,7 @@ static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev) { u32 tmp; - tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); - + tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; @@ -211,14 +210,14 @@ static void nbio_v7_7_init_registers(struct amdgpu_device *adev) { uint32_t def, data; - def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3); - data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3, - CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); - data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3, - CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); + def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3); + data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3, + CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); + data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3, + CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); - if (def != data) - WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data); + if (def != data) + WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data); } |