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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-12-14 11:47:37 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-12-14 11:47:37 -0800 |
commit | fab0fca1da5cdc48be051715cd9787df04fdce3a (patch) | |
tree | 5d1228cdd22bdd0675090349cf41aeef53e8a14c /drivers/staging/rtl8192u | |
parent | ae1985b50afaf76aaa09946ee36b59eaecb2ffae (diff) | |
parent | 7ea4d23293300ca2f225595849a4fe444fb80ea4 (diff) | |
download | linux-fab0fca1da5cdc48be051715cd9787df04fdce3a.tar.bz2 |
Merge tag 'media/v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab:
- some rework at the uAPI pixel format docs
- the smiapp driver has started to gain support for MIPI CSS camera
sensors and was renamed
- two new sensor drivers: ov02a10 and ov9734
- Meson gained a driver for the 2D acceleration unit
- Rockchip rkisp1 driver was promoted from staging
- Cedrus driver gained support for VP8
- two new remote controller keymaps were added
- the usual set of fixes cleanups and driver improvements
* tag 'media/v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (447 commits)
media: ccs: Add support for obtaining C-PHY configuration from firmware
media: ccs-pll: Print pixel rates
media: ccs: Print written register values
media: ccs: Add support for DDR OP SYS and OP PIX clocks
media: ccs-pll: Add support for DDR OP system and pixel clocks
media: ccs: Dual PLL support
media: ccs-pll: Add trivial dual PLL support
media: ccs-pll: Separate VT divisor limit calculation from the rest
media: ccs-pll: Fix VT post-PLL divisor calculation
media: ccs-pll: Make VT divisors 16-bit
media: ccs-pll: Rework bounds checks
media: ccs-pll: Print relevant information on PLL tree
media: ccs-pll: Better separate OP and VT sub-tree calculation
media: ccs-pll: Check for derating and overrating, support non-derating sensors
media: ccs-pll: Split off VT subtree calculation
media: ccs-pll: Add C-PHY support
media: ccs-pll: Add sanity checks
media: ccs-pll: Add support flexible OP PLL pixel clock divider
media: ccs-pll: Support two cycles per pixel on OP domain
media: ccs-pll: Add support for extended input PLL clock divider
...
Diffstat (limited to 'drivers/staging/rtl8192u')
0 files changed, 0 insertions, 0 deletions