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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-12-14 11:47:37 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-12-14 11:47:37 -0800 |
commit | fab0fca1da5cdc48be051715cd9787df04fdce3a (patch) | |
tree | 5d1228cdd22bdd0675090349cf41aeef53e8a14c /drivers/staging/media/sunxi/cedrus/cedrus.h | |
parent | ae1985b50afaf76aaa09946ee36b59eaecb2ffae (diff) | |
parent | 7ea4d23293300ca2f225595849a4fe444fb80ea4 (diff) | |
download | linux-fab0fca1da5cdc48be051715cd9787df04fdce3a.tar.bz2 |
Merge tag 'media/v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab:
- some rework at the uAPI pixel format docs
- the smiapp driver has started to gain support for MIPI CSS camera
sensors and was renamed
- two new sensor drivers: ov02a10 and ov9734
- Meson gained a driver for the 2D acceleration unit
- Rockchip rkisp1 driver was promoted from staging
- Cedrus driver gained support for VP8
- two new remote controller keymaps were added
- the usual set of fixes cleanups and driver improvements
* tag 'media/v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (447 commits)
media: ccs: Add support for obtaining C-PHY configuration from firmware
media: ccs-pll: Print pixel rates
media: ccs: Print written register values
media: ccs: Add support for DDR OP SYS and OP PIX clocks
media: ccs-pll: Add support for DDR OP system and pixel clocks
media: ccs: Dual PLL support
media: ccs-pll: Add trivial dual PLL support
media: ccs-pll: Separate VT divisor limit calculation from the rest
media: ccs-pll: Fix VT post-PLL divisor calculation
media: ccs-pll: Make VT divisors 16-bit
media: ccs-pll: Rework bounds checks
media: ccs-pll: Print relevant information on PLL tree
media: ccs-pll: Better separate OP and VT sub-tree calculation
media: ccs-pll: Check for derating and overrating, support non-derating sensors
media: ccs-pll: Split off VT subtree calculation
media: ccs-pll: Add C-PHY support
media: ccs-pll: Add sanity checks
media: ccs-pll: Add support flexible OP PLL pixel clock divider
media: ccs-pll: Support two cycles per pixel on OP domain
media: ccs-pll: Add support for extended input PLL clock divider
...
Diffstat (limited to 'drivers/staging/media/sunxi/cedrus/cedrus.h')
-rw-r--r-- | drivers/staging/media/sunxi/cedrus/cedrus.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h index 93c843ae14bb..e61c41853ba2 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h @@ -22,12 +22,16 @@ #include <media/videobuf2-v4l2.h> #include <media/videobuf2-dma-contig.h> +#include <linux/iopoll.h> #include <linux/platform_device.h> #define CEDRUS_NAME "cedrus" #define CEDRUS_CAPABILITY_UNTILED BIT(0) #define CEDRUS_CAPABILITY_H265_DEC BIT(1) +#define CEDRUS_CAPABILITY_H264_DEC BIT(2) +#define CEDRUS_CAPABILITY_MPEG2_DEC BIT(3) +#define CEDRUS_CAPABILITY_VP8_DEC BIT(4) #define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) @@ -35,6 +39,7 @@ enum cedrus_codec { CEDRUS_CODEC_MPEG2, CEDRUS_CODEC_H264, CEDRUS_CODEC_H265, + CEDRUS_CODEC_VP8, CEDRUS_CODEC_LAST, }; @@ -76,6 +81,10 @@ struct cedrus_h265_run { const struct v4l2_ctrl_hevc_slice_params *slice_params; }; +struct cedrus_vp8_run { + const struct v4l2_ctrl_vp8_frame_header *frame_params; +}; + struct cedrus_run { struct vb2_v4l2_buffer *src; struct vb2_v4l2_buffer *dst; @@ -84,6 +93,7 @@ struct cedrus_run { struct cedrus_h264_run h264; struct cedrus_mpeg2_run mpeg2; struct cedrus_h265_run h265; + struct cedrus_vp8_run vp8; }; }; @@ -135,6 +145,14 @@ struct cedrus_ctx { void *neighbor_info_buf; dma_addr_t neighbor_info_buf_addr; } h265; + struct { + unsigned int last_frame_p_type; + unsigned int last_filter_type; + unsigned int last_sharpness_level; + + u8 *entropy_probs_buf; + dma_addr_t entropy_probs_buf_dma; + } vp8; } codec; }; @@ -181,6 +199,7 @@ struct cedrus_dev { extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; extern struct cedrus_dec_ops cedrus_dec_ops_h264; extern struct cedrus_dec_ops cedrus_dec_ops_h265; +extern struct cedrus_dec_ops cedrus_dec_ops_vp8; static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) { @@ -192,6 +211,14 @@ static inline u32 cedrus_read(struct cedrus_dev *dev, u32 reg) return readl(dev->base + reg); } +static inline u32 cedrus_wait_for(struct cedrus_dev *dev, u32 reg, u32 flag) +{ + u32 value; + + return readl_poll_timeout_atomic(dev->base + reg, value, + (value & flag) == 0, 10, 1000); +} + static inline dma_addr_t cedrus_buf_addr(struct vb2_buffer *buf, struct v4l2_pix_format *pix_fmt, unsigned int plane) |