diff options
| author | Mark Brown <broonie@kernel.org> | 2022-11-25 21:26:29 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-11-25 21:26:29 +0000 |
| commit | acdce7aa7a4fc1094661feb0b833ae2eec2ad2d0 (patch) | |
| tree | 7b6654b2110f660651bae25728b5ab59227faa56 /drivers/spi/spi-intel.c | |
| parent | a6d99022e56e8c1ddc4c75895ed9e3ce5da88453 (diff) | |
| parent | bf0d29fb51ff5e6c13097dbfed7b99e0e35b4a15 (diff) | |
| download | linux-acdce7aa7a4fc1094661feb0b833ae2eec2ad2d0.tar.bz2 | |
fsi: Add regmap and refactor sbefifo
Merge series from Eddie James <eajames@linux.ibm.com>:
The SBEFIFO hardware can now be attached over a new I2C endpoint interface
called the I2C Responder (I2CR). In order to use the existing SBEFIFO
driver, add a regmap driver for the FSI bus and an endpoint driver for the
I2CR. Then, refactor the SBEFIFO and OCC drivers to clean up and use the
new regmap driver or the I2CR interface.
This branch just has the regmap change so it can be shared with the FSI
code.
Diffstat (limited to 'drivers/spi/spi-intel.c')
| -rw-r--r-- | drivers/spi/spi-intel.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c index 55f4ee2db002..3ac73691fbb5 100644 --- a/drivers/spi/spi-intel.c +++ b/drivers/spi/spi-intel.c @@ -52,17 +52,17 @@ #define FRACC 0x50 #define FREG(n) (0x54 + ((n) * 4)) -#define FREG_BASE_MASK 0x3fff +#define FREG_BASE_MASK GENMASK(14, 0) #define FREG_LIMIT_SHIFT 16 -#define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT) +#define FREG_LIMIT_MASK GENMASK(30, 16) /* Offset is from @ispi->pregs */ #define PR(n) ((n) * 4) #define PR_WPE BIT(31) #define PR_LIMIT_SHIFT 16 -#define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT) +#define PR_LIMIT_MASK GENMASK(30, 16) #define PR_RPE BIT(15) -#define PR_BASE_MASK 0x3fff +#define PR_BASE_MASK GENMASK(14, 0) /* Offsets are from @ispi->sregs */ #define SSFSTS_CTL 0x00 @@ -114,7 +114,7 @@ #define ERASE_OPCODE_SHIFT 8 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_SHIFT 16 -#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) +#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT) /* Flash descriptor fields */ #define FLVALSIG_MAGIC 0x0ff0a55a |