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authorJason-JH.Lin <jason-jh.lin@mediatek.com>2022-09-27 23:26:59 +0800
committerMatthias Brugger <matthias.bgg@gmail.com>2022-11-21 19:25:34 +0100
commitb237efd47df7d25b78c306e90b97c5aa0ff4c4fc (patch)
tree64bcb15a8586751926613a5eb40c51c4a4a85ca0 /drivers/soc
parente6c7e6216dc628ab7c627a6bcda7349715bbb67e (diff)
downloadlinux-b237efd47df7d25b78c306e90b97c5aa0ff4c4fc.tar.bz2
dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
For previous MediaTek SoCs, such as MT8173, there are 2 display HW pipelines binding to 1 mmsys with the same power domain, the same clock driver and the same mediatek-drm driver. For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 different power domains, different clock drivers and different mediatek-drm drivers. Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality) and they makes VDOSYS0 supports PQ function while they are not including in VDOSYS1. Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related component). It makes VDOSYS1 supports the HDR function while it's not including in VDOSYS0. To summarize0: Only VDOSYS0 can support PQ adjustment. Only VDOSYS1 can support HDR adjustment. Therefore, we need to separate these two different mmsys hardwares to 2 different compatibles for MT8195. Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding") Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220927152704.12018-2-jason-jh.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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