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| author | Michael Tretter <m.tretter@pengutronix.de> | 2021-01-21 08:16:50 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-02-08 18:31:25 -0800 |
| commit | f1bc982e7ceda6d0124ce65290727eaa49d0fd5a (patch) | |
| tree | e6c4da3f01b8928b897caa0b2c009daf2f3a2000 /drivers/soc/xilinx/Kconfig | |
| parent | 354dcf7b02a3755b662b148afb7d7ecf1fbbdf71 (diff) | |
| download | linux-f1bc982e7ceda6d0124ce65290727eaa49d0fd5a.tar.bz2 | |
soc: xilinx: vcu: implement PLL disable
The disabling of the PLL is not fully implemented, because according to
the ZynqMP register reference the RESET, POR_IN and PWR_POR bits have to
be set to bring the PLL into reset.
Set the bits to disable the PLL.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210121071659.1226489-7-m.tretter@pengutronix.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/soc/xilinx/Kconfig')
0 files changed, 0 insertions, 0 deletions