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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-02-07 22:21:42 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-02-08 14:29:39 +0200 |
| commit | 8271b2ef71aaabac452dc03a6cbe8960cbea4247 (patch) | |
| tree | 2cf522d43f154bc33dfcf0ffa2073f8407e4ede1 /drivers/soc/mediatek | |
| parent | 5f29ab23046a4bb08a850e41bdb579b2cb59421d (diff) | |
| download | linux-8271b2ef71aaabac452dc03a6cbe8960cbea4247.tar.bz2 | |
drm/i915: Track pipe csc enable in crtc state
Just like we did for pipe gamma, let's also track the pipe csc
state. The hardware only exists on ILK+, and currently we always
enable it on hsw+ and never on any other platforms. Just like
with pipe gamma, the primary plane control register is used
for the readout on pre-SKL, and the pipe bottom color register
on SKL+.
v2: Rebase
v3: Allow fastboot with csc_enable changes (Maarten)
Deal with HAS_GMCH
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-4-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/soc/mediatek')
0 files changed, 0 insertions, 0 deletions