diff options
| author | Rasmus Villemoes <linux@rasmusvillemoes.dk> | 2019-11-28 15:55:08 +0100 |
|---|---|---|
| committer | Li Yang <leoyang.li@nxp.com> | 2019-12-09 13:54:29 -0600 |
| commit | d9d95bcad38d18536ecf344e3f4105ed3c7dc7f7 (patch) | |
| tree | d606426d26238b77adc6e121c00c6e88ef03aebe /drivers/soc/fsl/qe | |
| parent | cf037a9b7af615f0543afae5daf2954a246ad321 (diff) | |
| download | linux-d9d95bcad38d18536ecf344e3f4105ed3c7dc7f7.tar.bz2 | |
soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers
Make it clear that these operate on big-endian registers (i.e. use the
iowrite*be primitives) before we introduce more uses of them and allow
the QE drivers to be built for platforms other than ppc32.
Reviewed-by: Timur Tabi <timur@kernel.org>
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Diffstat (limited to 'drivers/soc/fsl/qe')
| -rw-r--r-- | drivers/soc/fsl/qe/ucc.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c index 024d239ac1e1..ae9f2cf560cb 100644 --- a/drivers/soc/fsl/qe/ucc.c +++ b/drivers/soc/fsl/qe/ucc.c @@ -540,8 +540,8 @@ int ucc_set_tdm_rxtx_clk(u32 tdm_num, enum qe_clock clock, cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l : &qe_mux_reg->cmxsi1cr_h; - qe_clrsetbits32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift, - clock_bits << shift); + qe_clrsetbits_be32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift, + clock_bits << shift); return 0; } @@ -650,9 +650,9 @@ int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock, shift = ucc_get_tdm_sync_shift(mode, tdm_num); - qe_clrsetbits32(&qe_mux_reg->cmxsi1syr, - QE_CMXUCR_TX_CLK_SRC_MASK << shift, - source << shift); + qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr, + QE_CMXUCR_TX_CLK_SRC_MASK << shift, + source << shift); return 0; } |