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| author | Stanley Chu <stanley.chu@mediatek.com> | 2020-06-01 18:46:45 +0800 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2020-06-15 23:06:41 -0400 |
| commit | 561e3a8726b2dd94ce75cad6c9cab211551f368a (patch) | |
| tree | 0914f11a4c662b380fe7b5096faea4faa180562f /drivers/scsi/ufs/ufs-mediatek.h | |
| parent | 488edafb1120f715bebd80b6fe4089f83fb082b2 (diff) | |
| download | linux-561e3a8726b2dd94ce75cad6c9cab211551f368a.tar.bz2 | |
scsi: ufs-mediatek: Fix unbalanced clock on/off
MediaTek UFS clocks are separated to two parts and controlled by different
modules: ufs-mediatek and phy-ufs-mediatek.
If both Auto-Hibern8 and clk-gating feature are enabled, mphy power control
is not balanced thus unbalanced control also happens to the clocks probed
by phy-ufs-mediatek module.
Fix this issue by:
- Promise usage of phy_power_on/off balanced
- Remove phy_power_on/off control in suspend/resume vops since both can be
handled in setup_clock vops only
Link: https://lore.kernel.org/r/20200601104646.15436-5-stanley.chu@mediatek.com
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/ufs/ufs-mediatek.h')
| -rw-r--r-- | drivers/scsi/ufs/ufs-mediatek.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h index fc42dcbfd800..6052ec105aba 100644 --- a/drivers/scsi/ufs/ufs-mediatek.h +++ b/drivers/scsi/ufs/ufs-mediatek.h @@ -91,6 +91,7 @@ enum { struct ufs_mtk_host { struct ufs_hba *hba; struct phy *mphy; + bool mphy_powered_on; bool unipro_lpm; bool ref_clk_enabled; u16 ref_clk_ungating_wait_us; |