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authorSerge Semin <Sergey.Semin@baikalelectronics.ru>2022-09-30 01:53:58 +0300
committerStephen Boyd <sboyd@kernel.org>2022-09-30 14:19:31 -0700
commit081a9b7c74eae4e12b2cb1b86720f836a8f29247 (patch)
tree87efe3da10e0fe2c5201457e2178d245dba73742 /drivers/scsi/3w-sas.c
parente2eef312762e0b5a5a70d29fe59a245c0a3cffa0 (diff)
downloadlinux-081a9b7c74eae4e12b2cb1b86720f836a8f29247.tar.bz2
clk: baikal-t1: Add SATA internal ref clock buffer
It turns out the internal SATA reference clock signal will stay unavailable for the SATA interface consumer until the buffer on it's way is ungated. So aside with having the actual clock divider enabled we need to ungate a buffer placed on the signal way to the SATA controller (most likely some rudiment from the initial SoC release). Seeing the switch flag is placed in the same register as the SATA-ref clock divider at a non-standard ffset, let's implement it as a separate clock controller with the set-rate propagation to the parental clock divider wrapper. As such we'll be able to disable/enable and still change the original clock source rate. Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver") Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20220929225402.9696-5-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/scsi/3w-sas.c')
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