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| author | Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> | 2019-06-26 15:38:49 -0700 |
|---|---|---|
| committer | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2019-07-02 18:41:16 +0300 |
| commit | e765f37b9b8b4fa65682e9a78a2ca2b11d3d9096 (patch) | |
| tree | 40e08591bcf6445510a99f68a8a7c5a17e4cc24f /drivers/pwm | |
| parent | 71b21bd7f68a6ee59003f63d2e4f84fd9b0a8d07 (diff) | |
| download | linux-e765f37b9b8b4fa65682e9a78a2ca2b11d3d9096.tar.bz2 | |
platform/x86: ISST: Add Intel Speed Select PUNIT MSR interface
While using new non arhitectural features using PUNIT Mailbox and MMIO
read/write interface, still there is need to operate using MSRs to
control PUNIT. User space could have used user user-space MSR interface for
this, but when user space MSR access is disabled, then it can't. Here only
limited number of MSRs are allowed using this new interface.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'drivers/pwm')
0 files changed, 0 insertions, 0 deletions