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| author | Daniel Golle <daniel@makrotopia.org> | 2022-12-02 19:35:08 +0100 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@gmail.com> | 2022-12-06 12:46:04 +0100 |
| commit | aa3c668f2f98856af96e13f44da6ca4f26f0b98c (patch) | |
| tree | 8c95de41d5ffbcbddc985b36dcda7a8c2ab65fc1 /drivers/pwm | |
| parent | 07d8d8d29aa76f3c28020a9c914cc890eb86a48c (diff) | |
| download | linux-aa3c668f2f98856af96e13f44da6ca4f26f0b98c.tar.bz2 | |
pwm: mediatek: always use bus clock for PWM on MT7622
According to MT7622 Reference Manual for Development Board v1.0 the PWM
unit found in the MT7622 SoC also comes with the PWM_CK_26M_SEL register
at offset 0x210 just like other modern MediaTek ARM64 SoCs.
And also MT7622 sets that register to 0x00000001 on reset which is
described as 'Select 26M fix CLK as BCLK' in the datasheet.
Hence set has_ck_26m_sel to true also for MT7622 which results in the
driver writing 0 to the PWM_CK_26M_SEL register which is described as
'Select bus CLK as BCLK'.
Fixes: 0c0ead76235db0 ("pwm: mediatek: Always use bus clock")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Link: https://lore.kernel.org/r/Y1iF2slvSblf6bYK@makrotopia.org
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
| -rw-r--r-- | drivers/pwm/pwm-mediatek.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 6901a44dc428..a337b47dc2f7 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -296,7 +296,7 @@ static const struct pwm_mediatek_of_data mt6795_pwm_data = { static const struct pwm_mediatek_of_data mt7622_pwm_data = { .num_pwms = 6, .pwm45_fixup = false, - .has_ck_26m_sel = false, + .has_ck_26m_sel = true, }; static const struct pwm_mediatek_of_data mt7623_pwm_data = { |