diff options
author | JC Kuo <jckuo@nvidia.com> | 2021-01-20 15:34:04 +0800 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2021-06-03 14:49:33 +0200 |
commit | 2352fdb0d35e030089bf473b6e21b3f08895b33b (patch) | |
tree | 2d9f7664b504d707995a4ef56e33b1a95052b73f /drivers/pwm | |
parent | 23d5ec3f02866be6be3f47eab01771f1cf445a68 (diff) | |
download | linux-2352fdb0d35e030089bf473b6e21b3f08895b33b.tar.bz2 |
phy: tegra: xusb: Rearrange UPHY init on Tegra210
This commit is a preparation for enabling XUSB SC7 support.
It rearranges Tegra210 XUSB PADCTL UPHY initialization sequence,
for the following reasons:
1. PLLE hardware power sequencer has to be enabled only after both
PEX UPHY PLL and SATA UPHY PLL are initialized.
tegra210_uphy_init() -> tegra210_pex_uphy_enable()
-> tegra210_sata_uphy_enable()
-> tegra210_plle_hw_sequence_start()
-> tegra210_aux_mux_lp0_clamp_disable()
2. At cold boot and SC7 exit, the following bits must be cleared after
PEX/SATA lanes are out of IDDQ (IDDQ_DISABLE=1).
a. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN,
b. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY
c. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN
tegra210_pex_uphy_enable() and tegra210_sata_uphy_enable() are in
charge of bringing lanes out of IDDQ, and then AUX_MUX_LP0_* bits
will be cleared by tegra210_aux_mux_lp0_clamp_disable().
3. Once UPHY PLL hardware power sequencer is enabled, do not assert
reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-By: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/pwm')
0 files changed, 0 insertions, 0 deletions