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| author | Steven Price <steven.price@arm.com> | 2022-11-10 11:45:48 +0000 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@gmail.com> | 2022-11-11 15:03:59 +0100 |
| commit | dd1f1da4ada5d8ac774c2ebe97230637820b3323 (patch) | |
| tree | cffc4eb37456e1652795176066bb949698a7ff30 /drivers/pwm/pwm-tegra.c | |
| parent | 5eccd0d9fabc4d2ab8d2a0c056fb1d7e2ff892fc (diff) | |
| download | linux-dd1f1da4ada5d8ac774c2ebe97230637820b3323.tar.bz2 | |
pwm: tegra: Fix 32 bit build
The value of NSEC_PER_SEC << PWM_DUTY_WIDTH doesn't fix within a 32 bit
integer causing a build warning/error (and the value truncated):
drivers/pwm/pwm-tegra.c: In function ‘tegra_pwm_config’:
drivers/pwm/pwm-tegra.c:148:53: error: result of ‘1000000000 << 8’ requires 39 bits to represent, but ‘long int’ only has 32 bits [-Werror=shift-overflow=]
148 | required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH,
| ^~
Explicitly cast to a u64 to ensure the correct result.
Fixes: cfcb68817fb3 ("pwm: tegra: Improve required rate calculation")
Signed-off-by: Steven Price <steven.price@arm.com>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Diffstat (limited to 'drivers/pwm/pwm-tegra.c')
| -rw-r--r-- | drivers/pwm/pwm-tegra.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 6fc4b69a3ba7..249dc0193297 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -145,7 +145,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * source clock rate as required_clk_rate, PWM controller will * be able to configure the requested period. */ - required_clk_rate = DIV_ROUND_UP_ULL(NSEC_PER_SEC << PWM_DUTY_WIDTH, + required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH, period_ns); if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) |