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| author | David S. Miller <davem@davemloft.net> | 2017-07-21 03:38:43 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-07-21 03:38:43 +0100 |
| commit | 7a68ada6ec7d88c68057d3a4c2a517eb94289976 (patch) | |
| tree | 51cd586e74fc92bfbdf382fa1544a235d908b25c /drivers/pwm/pwm-tegra.c | |
| parent | 760446f967678e14ee1b6464ee1bb8562f299fa6 (diff) | |
| parent | 96080f697786e0a30006fcbcc5b53f350fcb3e9f (diff) | |
| download | linux-7a68ada6ec7d88c68057d3a4c2a517eb94289976.tar.bz2 | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Diffstat (limited to 'drivers/pwm/pwm-tegra.c')
| -rw-r--r-- | drivers/pwm/pwm-tegra.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 8c6ed556db28..e9b33f09ff09 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -41,6 +41,9 @@ struct tegra_pwm_soc { unsigned int num_channels; + + /* Maximum IP frequency for given SoCs */ + unsigned long max_frequency; }; struct tegra_pwm_chip { @@ -201,7 +204,18 @@ static int tegra_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); - /* Read PWM clock rate from source */ + /* Set maximum frequency of the IP */ + ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); + return ret; + } + + /* + * The requested and configured frequency may differ due to + * clock register resolutions. Get the configured frequency + * so that PWM period can be calculated more accurately. + */ pwm->clk_rate = clk_get_rate(pwm->clk); pwm->rst = devm_reset_control_get(&pdev->dev, "pwm"); @@ -273,10 +287,12 @@ static int tegra_pwm_resume(struct device *dev) static const struct tegra_pwm_soc tegra20_pwm_soc = { .num_channels = 4, + .max_frequency = 48000000UL, }; static const struct tegra_pwm_soc tegra186_pwm_soc = { .num_channels = 1, + .max_frequency = 102000000UL, }; static const struct of_device_id tegra_pwm_of_match[] = { |